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NUC505 芯片内部Flash读写问题

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huangbbb2010|  楼主 | 2015-12-3 17:39 | 显示全部楼层 |阅读模式
用官方提供的SPIM_DMA例程在仿真环境下跑是正常的,但烧到芯片上就跑不起来。我用的是IAR开发环境,有修改过link文件,但还是跑不起来。好像每次跑到spim_open后程序就死掉了。有谁读写过内部Flash的?有没有什么建议和方法。谢谢
wangwang2015| | 2015-12-3 18:06 | 显示全部楼层
我们公司有技术支持,但是要加FAE QQ:2355898184,他可以帮你解决技术上问题。

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奥德赛| | 2015-12-3 20:19 | 显示全部楼层
是不是延时时间不够呢?

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yutianxiang618| | 2015-12-3 22:01 | 显示全部楼层
是的,我同事也遇到这个相同的问题,仿真正常,下载就跑不动了

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quray1985| | 2015-12-5 19:59 | 显示全部楼层
把那段代码贴出来瞧瞧

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huangbbb2010|  楼主 | 2015-12-7 09:31 | 显示全部楼层
quray1985 发表于 2015-12-5 19:59
把那段代码贴出来瞧瞧

程序其实是新唐官方网站下载的,NUC505参考例程SPIM_DMA。
void SYS_Init(void)
{      
    /* Enable  XTAL */
    CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
   
    /* Enable IP clock */
    CLK_EnableModuleClock(UART0_MODULE);
    CLK_EnableModuleClock(SPIM_MODULE);
    //CLK->APBCLK = CLK_APBCLK_UART0CKEN_Msk;     // Enable UART0 IP clock.
    //CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;     // Enable SPIM IP clock.

    /* Select IP clock source */
    /* PCLK divider = 1 (/2) */
    CLK_SetModuleClock(PCLK_MODULE, 0, 1);
    /* UART0 clock source = XIN */
    CLK_SetModuleClock(UART0_MODULE, CLK_UART0_SRC_EXT, 0);
    //CLK->CLKDIV3 &= ~(CLK_CLKDIV3_UART0DIV_Msk | CLK_CLKDIV3_UART0SEL_Msk);
   
    /* Update System Core Clock */
    CLK_SetCoreClock(100000000);
    SystemCoreClockUpdate();
   
    /* Init I/O multi-function pins */
    /* Configure multi-function pins for UART0 RXD and TXD */
        SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB0MFP_Msk) ) | SYS_GPB_MFPL_PB0MFP_UART0_TXD;
        SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB1MFP_Msk) ) | SYS_GPB_MFPL_PB1MFP_UART0_RXD;
    /* Configure multi-function pins for SPIM, Slave I/F=GPIO. */      
}

uint32_t SPIM_Open(SPIM_T *spim, uint32_t u32SPIMode, uint32_t u32BusClock)
{
#if 0   // User program will take care.
    CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;     // Enable IP clock.
#endif
        //程序执行下面这一行就死机了
    SYS->IPRST1 |= SYS_IPRST1_SPIMRST_Msk;      // Reset IP.
    SYS->IPRST1 &= ~SYS_IPRST1_SPIMRST_Msk;
    SPIM_SetIF(spim, SPIM_CTL1_IFSEL_INTERN);   
    return SPIM_SetBusClock(spim, u32BusClock);
}

void TestDMAMode(void)
{   
    SPIM_Open(SPIM, 0, SPI_BUS_CLK);               
    DoDMASnglTest();        // 1-bit DMA Read/Write test.   
    SPIM_Close(SPIM);   
}  

int main(void)
{   
    SYS_Init();   
    UART_Open(UART0, 115200);   
    TestDMAMode();      // Test SPIM DMA mode.   
    while (1);
    //return 0;
}

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huangcunxiake| | 2015-12-7 19:32 | 显示全部楼层
新唐科技凭借多年优异的Cortex®-M MCU经验,最新力推带有24-bit Audio Codec及高容量128KB内存新产品Cortex®-M4 NuMicro™ NUC505系列。不同于市面上昂贵的DSP芯片,NUC505系列提供了高性价比Cortex®-M4 DSP芯片之首选。NUC505系列以ARM Cortex®-M4核心,搭配DSP(数字信号处理器)与FPU(浮点运算单元),运行速度高达100 MHz,内置128 KB 内存以及2 MB SPI Flash并支持4-bit数据快速传输,可满足复杂算法的应用。 高效能之NUC505系列更结合了新唐独有的外挂储存设备保护机制(PMOC),可有效保护客户开发之程序。此外,NUC505系列具备了丰富外设,涵盖USB HS Device、USB FS Host、I²S、12-bit ADC、RTC、2组I²C、3组UART等,极适合于消费电子、iPhone周边产品、物联网、云端与音频产品等等应用需求。

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huangcunxiake| | 2015-12-7 20:02 | 显示全部楼层
/**************************************************************************//**
* [url=home.php?mod=space&uid=288409]@file[/url]        spim.h
* [url=home.php?mod=space&uid=895143]@version[/url]     V1.00
* $Revision:   1$
* $Date:       14/07/10 5:00p$
* [url=home.php?mod=space&uid=247401]@brief[/url]       NUC505 series SPIM driver header file
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPIM_H__
#define __SPIM_H__

#ifdef __cplusplus
extern "C"
{
#endif


/** @addtogroup NUC505_Device_Driver NUC505 Device Driver
  @{
*/

/** @addtogroup NUC505_SPIM_Driver SPIM Driver
  @{
*/

/** @addtogroup NUC505_SPIM_EXPORTED_CONSTANTS SPIM Exported Constants
  @{
*/

#define SPIM_CTL0_BITMODE_STAN      (0UL << SPIM_CTL0_BITMODE_Pos)              /*!< Standard mode (SPI Interface including DO, DI, HOLD, WP). \hideinitializer */
#define SPIM_CTL0_BITMODE_DUAL      (1UL << SPIM_CTL0_BITMODE_Pos)              /*!< Dual mode (SPI Interface including D0, D1, HOLD, WP). \hideinitializer */
#define SPIM_CTL0_BITMODE_QUAD      (2UL << SPIM_CTL0_BITMODE_Pos)              /*!< Quad mode (SPI Interface including D0, D1, D2, D3). \hideinitializer */
#define SPIM_CTL0_OPMODE_IO         (0UL << SPIM_CTL0_OPMODE_Pos)               /*!< I/O Mode. \hideinitializer */
#define SPIM_CTL0_OPMODE_DMAWRITE   (1UL << SPIM_CTL0_OPMODE_Pos)               /*!< DMA Write mode. \hideinitializer */
#define SPIM_CTL0_OPMODE_DMAREAD    (2UL << SPIM_CTL0_OPMODE_Pos)               /*!< DMA Read mode. \hideinitializer */
#define SPIM_CTL0_OPMODE_DMM        (3UL << SPIM_CTL0_OPMODE_Pos)               /*!< Direct Memory Mapping mode. \hideinitializer */
#define SPIM_CTL0_CMDCODE_PAGE_PROG                 (0x02UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Page Program command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE1      (0x32UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Quad Page Program (type 1) command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE2      (0x38UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Quad Page Program (type 2) command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE3      (0x40UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Quad Page Program (type 3) command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_READ_DATA                 (0x03UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Read Data command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_FAST_READ                 (0x0BUL << SPIM_CTL0_CMDCODE_Pos)   /*!< Fast Read command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_FAST_READ_DUAL_OUT        (0x3BUL << SPIM_CTL0_CMDCODE_Pos)   /*!< Fast Read Dual Output command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */
#define SPIM_CTL0_CMDCODE_FAST_READ_QUAD_IO         (0xEBUL << SPIM_CTL0_CMDCODE_Pos)   /*!< Fast Read Quad I/O command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */

#define SPIM_CTL1_IFSEL_GPIO        (0UL << SPIM_CTL1_IFSEL_Pos)                /*!< SPI Interface from GPIO. \hideinitializer */
#define SPIM_CTL1_IFSEL_MCP         (1UL << SPIM_CTL1_IFSEL_Pos)                /*!< SPI Interface from MCP. \hideinitializer */
#define SPIM_CTL1_IFSEL_MCP64       (2UL << SPIM_CTL1_IFSEL_Pos)                /*!< SPI Interface from MCP64. \hideinitializer */
#define SPIM_CTL1_IFSEL_INTERN      SPIM_CTL1_IFSEL_MCP                         /*!< SPI Interface from internal(MCP/MCP64). \hideinitializer */
#define SPIM_CTL1_IFSEL_EXTERN      SPIM_CTL1_IFSEL_GPIO                        /*!< SPI Interface from external(GPIO). \hideinitializer */

/* SPIM Interrupt Mask */
#define SPIM_INT_MASK                   (0x001)                                 /*!< Interrupt mask. \hideinitializer */


/*@}*/ /* end of group NUC505_SPIM_EXPORTED_CONSTANTS */

/** @addtogroup NUC505_SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions
  @{
*/

/**
  * @brief                  Enable I/O mode.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32BitMode  Bit mode. Valid values include:
  *                         - \ref SPIM_CTL0_BITMODE_STAN
  *                         - \ref SPIM_CTL0_BITMODE_DUAL
  *                         - \ref SPIM_CTL0_BITMODE_QUAD
  * @param[in]  u32QDIODir  I/O direction for Quad/Dual mode. Valid values can be 0 (for input) or 1 (for output).
  * [url=home.php?mod=space&uid=266161]@return[/url]                 None.
  * \hideinitializer
  */
#define SPIM_ENABLE_IO_MODE(spim, u32BitMode, u32QDIODir) \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_BITMODE_Msk))) | (u32BitMode);   \
        (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_QDIODIR_Msk))) | ((u32QDIODir) << SPIM_CTL0_QDIODIR_Pos);   \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | SPIM_CTL0_OPMODE_IO;    \
    } while (0)

/**
  * @brief                  Set bit mode for I/O mode.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32BitMode  Bit mode. Valid values include:
  *                         - \ref SPIM_CTL0_BITMODE_STAN
  *                         - \ref SPIM_CTL0_BITMODE_DUAL
  *                         - \ref SPIM_CTL0_BITMODE_QUAD
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_SET_BIT_MODE(spim, u32BitMode)  \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_BITMODE_Msk))) | (u32BitMode);    \
    } while (0)

/**
  * @brief                  Set direction for Quad/Dual I/O mode.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32Dir      Direction. Valid values can be 0 (for input) and 1 (for output).
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_SET_QDIODIR(spim, u32Dir)  \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_QDIODIR_Msk))) | (((u32Dir) ? 1 : 0) << SPIM_CTL0_QDIODIR_Pos);    \
    } while (0)


/**
  * @brief                  Enable DMA mode.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  isWrite     0 for DMA Read mode; 1 for DMA Write mode.
  * @param[in]  u32CmdCode  Command code.
  * - Valid values for DMA Write mode include:
  *     - \ref SPIM_CTL0_CMDCODE_PAGE_PROG
  *     - \ref SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE1
  *     - \ref SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE2
  *     - \ref SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE3
  * - Valid values for DMA Read mode include:
  *     - \ref SPIM_CTL0_CMDCODE_READ_DATA
  *     - \ref SPIM_CTL0_CMDCODE_FAST_READ
  *     - \ref SPIM_CTL0_CMDCODE_FAST_READ_DUAL_OUT
  *     - \ref SPIM_CTL0_CMDCODE_FAST_READ_QUAD_IO
  * @param[in]  is4ByteAddr 4-byte address or not.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_ENABLE_DMA_MODE(spim, isWrite, u32CmdCode, is4ByteAddr) \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (u32CmdCode);  \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | ((is4ByteAddr) << SPIM_CTL0_B4ADDREN_Pos);    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (isWrite ? SPIM_CTL0_OPMODE_DMAWRITE : SPIM_CTL0_OPMODE_DMAREAD);    \
    } while (0)

/**
  * @brief                  Enable Direct Memory Mapping (DMM) mode.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32ReadCmdCode  Read command code. Valid values include:
  *                         - \ref SPIM_CTL0_CMDCODE_READ_DATA
  *                         - \ref SPIM_CTL0_CMDCODE_FAST_READ
  *                         - \ref SPIM_CTL0_CMDCODE_FAST_READ_DUAL_OUT
  *                         - \ref SPIM_CTL0_CMDCODE_FAST_READ_QUAD_IO
  * @param[in]  is4ByteAddr 4-byte address or not.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_ENABLE_DMM_MODE(spim, u32ReadCmdCode, is4ByteAddr) \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (u32ReadCmdCode);  \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | ((is4ByteAddr) << SPIM_CTL0_B4ADDREN_Pos);    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (SPIM_CTL0_OPMODE_DMM);    \
    } while (0)

/**
  * @brief                      Set the length of suspend interval.
  * @param[in]  spim            Base address of SPIM module.
  * @param[in]  u32SuspCycle    Decides the length of suspend interval which ranges between 0 and 15.
  * @return                     None.
  * \hideinitializer
  */
#define SPIM_SET_SUSPEND_CYCLE(spim, u32SuspCycle) \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_SLEEP_Msk)) | ((u32SuspCycle) << SPIM_CTL0_SLEEP_Pos);    \
    } while (0)

/**
  * @brief                      Set the number of successive transmit/receive transactions in one transfer.
  * @param[in]  spim            Base address of SPIM module.
  * @param[in]  u32BurstNum     Decides the transmit/receive number in one transfer which ranges between 1 and 4.
  * @return                     None.
  * \hideinitializer
  */
#define SPIM_SET_BURST_NUM(spim, u32BurstNum) \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((u32BurstNum) - 1) << SPIM_CTL0_BURSTNUM_Pos);  \
    } while (0)

/**
  * @brief                  Set the data width of a transmit/receive transaction.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32Width    Data width which ranges between 1 and 32.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_SET_DATA_WIDTH(spim, u32Width)   \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((u32Width) - 1) << SPIM_CTL0_DWIDTH_Pos);  \
    } while (0)

/**
  * @brief              Disable cipher.
  * [url=home.php?mod=space&uid=536309]@NOTE[/url]               Cipher can only be disabled and cannot be enabled.
  * @param[in]  spim    Base address of SPIM module.
  * @return             None.
  * \hideinitializer
  */
#define SPIM_DISABLE_CIPHER(spim) \
    do {    \
        (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_CipherDis_Msk)) | ((! (0)) << SPIM_CTL0_CipherDis_Pos); \
    } while (0)

/**
  * @brief              Set slave select pin to high state.
  * @param[in]  spim    Base address of SPIM module.
  * @return             None.
  * \hideinitializer
  */
#define SPIM_SET_SS_HIGH(spim) \
    do {    \
        ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((0) << SPIM_CTL1_SSACTPOL_Pos));   \
        ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (0)) << SPIM_CTL1_SS_Pos)); \
    } while (0)

/**
  * @brief              Set slave select pin to low state.
  * @param[in]  spim    Base address of SPIM module.
  * @return             None.
  * \hideinitializer
  */
#define SPIM_SET_SS_LOW(spim) \
    do {    \
        ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((0) << SPIM_CTL1_SSACTPOL_Pos));   \
        ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (1)) << SPIM_CTL1_SS_Pos)); \
    } while (0)

/**
  * @brief              Check if SPIM module is busy.
  * @param[in]  spim    Base address of SPIM module.
  * @retval 0           Not busy.
  * @retval 1           Busy.
  * \hideinitializer
  */
#define SPIM_IS_BUSY(spim) \
    (!!((spim)->CTL1 & SPIM_CTL1_SPIMEN_Msk))

/**
  * @brief              Trigger SPI transfer.
  * @param[in]  spim    Base address of SPIM module.
  * @return             None.
  * \hideinitializer
  */
#define SPIM_TRIGGER(spim)  \
    do {    \
        (spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SPIMEN_Msk)) | SPIM_CTL1_SPIMEN_Msk;   \
    } while (0)

/**
  * @brief                  Write datum to TX0 register.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_WRITE_TX0(spim, u32TxData)   \
    do {    \
        (spim)->TX0 = u32TxData;  \
    } while (0)

/**
  * @brief                  Write datum to TX1 register.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_WRITE_TX1(spim, u32TxData)   \
    do {    \
        (spim)->TX1 = u32TxData;  \
    } while (0)

/**
  * @brief                  Write datum to TX2 register.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_WRITE_TX2(spim, u32TxData)   \
    do {    \
        (spim)->TX2 = u32TxData;  \
    } while (0)

/**
  * @brief                  Write datum to TX3 register.
  * @param[in]  spim        Base address of SPIM module.
  * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  * @return                 None.
  * \hideinitializer
  */
#define SPIM_WRITE_TX3(spim, u32TxData)   \
    do {    \
        (spim)->TX3 = u32TxData;  \
    } while (0)

/**
  * @brief                  Get the datum read from RX0 register.
  * @param[in]  spim        Base address of SPIM module.
  * @return                 Datum read from RX0 register.
  * \hideinitializer
  */
#define SPIM_READ_RX0(spim)     (spim)->RX0

/**
  * @brief                  Get the datum read from RX1 register.
  * @param[in]  spim        Base address of SPIM module.
  * @return                 Datum read from RX1 register.
  * \hideinitializer
  */
#define SPIM_READ_RX1(spim)     (spim)->RX1

/**
  * @brief                  Get the datum read from RX2 register.
  * @param[in]  spim        Base address of SPIM module.
  * @return                 Datum read from RX2 register.
  * \hideinitializer
  */
#define SPIM_READ_RX2(spim)     (spim)->RX2

/**
  * @brief                  Get the datum read from RX3 register.
  * @param[in]  spim        Base address of SPIM module.
  * @return                 Datum read from RX3 register.
  * \hideinitializer
  */
#define SPIM_READ_RX3(spim)     (spim)->RX3

uint32_t SPIM_Open(SPIM_T *spim, uint32_t u32SPIMode, uint32_t u32BusClock);
void SPIM_Close(SPIM_T *spim);
uint32_t SPIM_SetBusClock(SPIM_T *spim, uint32_t u32BusClock);
uint32_t SPIM_GetBusClock(SPIM_T *spim);
void SPIM_EnableInt(SPIM_T *spim, uint32_t u32Mask);
void SPIM_DisableInt(SPIM_T *spim, uint32_t u32Mask);
uint32_t SPIM_GetIntFlag(SPIM_T *spim, uint32_t u32Mask);
void SPIM_ClearIntFlag(SPIM_T *spim, uint32_t u32Mask);
void SPIM_SetIF(SPIM_T *spim, uint32_t u32IFSel);

void SPIM_DMAWritePage(SPIM_T *spim, uint32_t u32FlashAddr, uint32_t u32Len, uint8_t *pu8TxBuf);
void SPIM_DMAReadFlash(SPIM_T *spim, uint32_t u32FlashAddr, uint32_t u32Len, uint8_t *pu8RxBuf);

/*@}*/ /* end of group NUC505_SPIM_EXPORTED_FUNCTIONS */

/*@}*/ /* end of group NUC505_SPIM_Driver */

/*@}*/ /* end of group NUC505_Device_Driver */

#ifdef __cplusplus
}
#endif

#endif //__SPIM_H__

/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/


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huangcunxiake| | 2015-12-7 20:02 | 显示全部楼层
QQ截图20151204091454.png
不知道这是个什么图,有人知道没

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史迪威将军| | 2015-12-7 20:56 | 显示全部楼层
有可能是复位电路有问题,仿真的时候是软复位吧

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C洛达尔多| | 2015-12-9 20:34 | 显示全部楼层
感觉是硬件的复位电路没处理好

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zhuotuzi| | 2015-12-9 20:51 | 显示全部楼层
带有24-bit Audio Codec及高容量128KB内存新产品Cortex®-M4 NuMicro™ NUC505系列。不同于市面上昂贵的DSP芯片,NUC505系列提供了高性价比Cortex®-M4 DSP芯片之首选。

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Beckham_Owen| | 2015-12-12 21:37 | 显示全部楼层
楼主问题解决了吗,我这里也有人遇到了同样的问题

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捉虫天师| | 2016-6-19 22:04 | 显示全部楼层
啥问题,好多人不会啊。

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捉虫天师| | 2016-6-19 22:15 | 显示全部楼层
/**************************************************************************//**
* [url=home.php?mod=space&uid=288409]@file[/url]     main.c
* [url=home.php?mod=space&uid=895143]@version[/url]  V2.0
* $Revision: 11 $
* $Date: 15/03/04 9:47a $
* [url=home.php?mod=space&uid=247401]@brief[/url]    Access the SPI Flash through a SPI interface.
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "NUC505Series.h"

#define TEST_NUMBER 1   /* page numbers */
#define TEST_LENGTH 256 /* length */

#define SPI_FLASH_PORT  SPI0

uint8_t SrcArray[TEST_LENGTH];
uint8_t DestArray[TEST_LENGTH];

/* Function prototype declaration */
void SYS_Init(void);
void UART0_Init(void);
void SPI0_Init(void);

uint16_t SpiFlash_ReadMidDid(void)
{
    uint8_t u8RxData[6], u8IDCnt = 0;

    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x90, Read Manufacturer/Device ID
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x90);

    // send 24-bit '0', dummy
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);

    // receive 16-bit
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);

    while(!SPI_GET_RX_FIFO_EMPTY_FLAG(SPI_FLASH_PORT))
        u8RxData[u8IDCnt ++] = SPI_READ_RX(SPI_FLASH_PORT);

    return ( (u8RxData[4]<<8) | u8RxData[5] );
}

void SpiFlash_ChipErase(void)
{
    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x06, Write enable
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);

    //////////////////////////////////////////

    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0xC7, Chip Erase
    SPI_WRITE_TX(SPI_FLASH_PORT, 0xC7);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);

    SPI_ClearRxFIFO(SPI0);
}

uint8_t SpiFlash_ReadStatusReg(void)
{
    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x05, Read status register
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x05);

    // read status
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);

    // skip first rx data
    SPI_READ_RX(SPI_FLASH_PORT);

    return (SPI_READ_RX(SPI_FLASH_PORT) & 0xff);
}

void SpiFlash_WriteStatusReg(uint8_t u8Value)
{
    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x06, Write enable
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);

    ///////////////////////////////////////

    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x01, Write status register
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x01);

    // write status
    SPI_WRITE_TX(SPI_FLASH_PORT, u8Value);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);
}

void SpiFlash_WaitReady(void)
{
    uint8_t ReturnValue;

    do {
        ReturnValue = SpiFlash_ReadStatusReg();
        ReturnValue = ReturnValue & 1;
    } while(ReturnValue!=0); // check the BUSY bit
}

void SpiFlash_NormalPageProgram(uint32_t StartAddress, uint8_t *u8DataBuffer)
{
    uint32_t i = 0;

    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x06, Write enable
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);


    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x02, Page program
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x02);

    // send 24-bit start address
    SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
    SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8)  & 0xFF);
    SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress       & 0xFF);

    // write data
    while(1) {
        if(!SPI_GET_TX_FIFO_FULL_FLAG(SPI_FLASH_PORT)) {
            SPI_WRITE_TX(SPI_FLASH_PORT, u8DataBuffer[i++]);
            if(i >= 255) break;
        }
    }

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);

    SPI_ClearRxFIFO(SPI_FLASH_PORT);
}

void SpiFlash_NormalRead(uint32_t StartAddress, uint8_t *u8DataBuffer)
{
    uint32_t i;

    // /CS: active
    SPI_SET_SS_LOW(SPI_FLASH_PORT);

    // send Command: 0x03, Read data
    SPI_WRITE_TX(SPI_FLASH_PORT, 0x03);

    // send 24-bit start address
    SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
    SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8)  & 0xFF);
    SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress       & 0xFF);

    while(SPI_IS_BUSY(SPI_FLASH_PORT));
    // clear RX buffer
    SPI_ClearRxFIFO(SPI_FLASH_PORT);

    // read data
    for(i=0; i<256; i++) {
        SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
        while(SPI_IS_BUSY(SPI_FLASH_PORT));
        u8DataBuffer[i] = SPI_READ_RX(SPI_FLASH_PORT);
    }

    // wait tx finish
    while(SPI_IS_BUSY(SPI_FLASH_PORT));

    // /CS: de-active
    SPI_SET_SS_HIGH(SPI_FLASH_PORT);
}

/* Main */
int main(void)
{
    uint32_t u32ByteCount, u32FlashAddress, u32PageNumber;
    uint32_t nError = 0;
    uint16_t u16ID;

    /* Init System, IP clock and multi-function I/O */
    SYS_Init();

    /* Init UART0 to 115200-8n1 for print message */
    UART0_Init();

                /* Init SPI0, IP clock and multi-function I/O */
                SPI0_Init();
               
    /* Configure SPI_FLASH_PORT as a master, MSB first, 8-bit transaction, SPI Mode-0 timing, clock is 2MHz */
    SPI_Open(SPI_FLASH_PORT, SPI_MASTER, SPI_MODE_0, 8, 2000000);

    /* Enable the automatic hardware slave select function. Select the SS0 pin and configure as low-active. */
    SPI_EnableAutoSS(SPI_FLASH_PORT, SPI_SS, SPI_SS_ACTIVE_LOW);
    SPI_ENABLE(SPI_FLASH_PORT);

    printf("\n+------------------------------------------------------------------------+\n");
    printf("|            NUC505        SPI Sample with SPI Flash                     |\n");
    printf("+------------------------------------------------------------------------+\n");

    /* Wait ready */
    SpiFlash_WaitReady();

///    if((u16ID = SpiFlash_ReadMidDid()) != 0x1C14) {
                if((u16ID = SpiFlash_ReadMidDid()) != 0xEF14) {
        printf("Wrong ID, 0x%x\n", u16ID);
        return -1;
    } else
        printf("Flash found: Winbond 25Q16OVSEG ...\n");

    printf("Erase chip ...");

    /* Erase SPI flash */
    SpiFlash_ChipErase();

    /* Wait ready */
    SpiFlash_WaitReady();

    printf("[OK]\n");

    /* init source data buffer */
    for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
        SrcArray[u32ByteCount] = u32ByteCount;
    }

    printf("Start to normal write data to Flash ...");
    /* Program SPI flash */
    u32FlashAddress = 0;
    for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++) {
        /* page program */
        SpiFlash_NormalPageProgram(u32FlashAddress, SrcArray);
        SpiFlash_WaitReady();
        u32FlashAddress += 0x100;
    }

    printf("[OK]\n");

    /* clear destination data buffer */
    for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
        DestArray[u32ByteCount] = 0;
    }

    printf("Normal Read & Compare ...");

    /* Read SPI flash */
    u32FlashAddress = 0;
    for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++) {
        /* page read */
        SpiFlash_NormalRead(u32FlashAddress, DestArray);
        u32FlashAddress += 0x100;

        for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
            if(DestArray[u32ByteCount] != SrcArray[u32ByteCount])
                nError ++;
        }
    }

    if(nError == 0)
        printf("[OK]\n");
    else
        printf("[FAIL]\n");

    while(1);
}

void SYS_Init(void)
{

/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock                                                                                       */
/*---------------------------------------------------------------------------------------------------------*/
    /* Unlock protected registers */
    //SYS_UnlockReg();
     
    /* Enable  XTAL */
    CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;

    CLK_SetCoreClock(FREQ_96MHZ);
   
                /* PCLK divider */
                CLK_SetModuleClock(PCLK_MODULE, NULL, 1);
               
    /* Lock protected registers */
    //SYS_LockReg();
        
}

void UART0_Init(void)
{
                /* Enable UART0 Module clock */
    CLK_EnableModuleClock(UART0_MODULE);
                /* UART0 module clock from EXT */
                CLK_SetModuleClock(UART0_MODULE, CLK_UART0_SRC_EXT, 0);
    /* Reset IP */
    SYS_ResetModule(UART0_RST);   
    /* Configure UART0 and set UART0 Baud-rate */
                UART_Open(UART0, 115200);
                /*---------------------------------------------------------------------------------------------------------*/
    /* Init I/O Multi-function                                                                                 */
    /*---------------------------------------------------------------------------------------------------------*/
    /* Configure multi-function pins for UART0 RXD and TXD */
                SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB0MFP_Msk) ) | SYS_GPB_MFPL_PB0MFP_UART0_TXD;       
                SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB1MFP_Msk) ) | SYS_GPB_MFPL_PB1MFP_UART0_RXD;       
       
}

void SPI0_Init(void)
{
                /* Enable SPI0 Module clock */
    CLK_EnableModuleClock(SPI0_MODULE);
                /* SPI0 module clock from EXT */
                CLK_SetModuleClock(SPI0_MODULE, CLK_SPI0_SRC_PLL, 0);
    /* Reset IP */
    SYS_ResetModule(SPI0_RST);   
    /*---------------------------------------------------------------------------------------------------------*/
    /* Init I/O Multi-function                                                                                 */
    /*---------------------------------------------------------------------------------------------------------*/
    /* Configure multi-function pins for SPI0 */
                SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB2MFP_Msk) ) | SYS_GPB_MFPL_PB2MFP_SPI0_SS;       
                SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB3MFP_Msk) ) | SYS_GPB_MFPL_PB3MFP_SPI0_CLK;       
                SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB4MFP_Msk) ) | SYS_GPB_MFPL_PB4MFP_SPI0_MOSI;       
                SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB5MFP_Msk) ) | SYS_GPB_MFPL_PB5MFP_SPI0_MISO;       
       
}

/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/

这个是吧

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Qwo| | 2018-6-1 19:22 | 显示全部楼层
我也遇到这个问题了,楼主解决了吗?

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hijxyz| | 2019-5-9 13:39 | 显示全部楼层
我也遇到这个问题了,怎么就解决呢

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