借宝地用图图(搞了快几个星期了环境还是没有搭好!哎)

只看该作者 · 2009-8-19 22:58

smdk2440.c:29:21: error: s3c2440.h: No such file or directory
smdk2440.c: In function 'board_init':
smdk2440.c:70: error: 'S3C24X0_CLOCK_POWER' undeclared (first use in this function)
smdk2440.c:70: error: (Each undeclared identifier is reported only once
smdk2440.c:70: error: for each function it appears in.)
smdk2440.c:70: error: expected expression before 'const'
smdk2440.c:71: error: 'S3C24X0_GPIO' undeclared (first use in this function)
smdk2440.c:71: error: expected expression before 'const'
smdk2440.c:74: error: 'clk_power' undeclared (first use in this function)
smdk2440.c:89: error: 'gpio' undeclared (first use in this function)
make[1]: *** [smdk2440.o] 错误 1
make[1]:正在离开目录 `/home/zou/workspace/u-boot-2009.06/board/samsung/smdk2440'
make: *** [board/samsung/smdk2440/libsmdk2440.a] 错误 2
zou@zou-desktop:~/桌面/workspace/u-boot-2009.06$

只看该作者 · 2009-8-20 00:17

make smdk2410_config
make ARCH=arm

只看该作者 · 2009-8-21 00:27

2440(1)OK

post.a board/samsung/smdk2440/libsmdk2440.a --end-group -L /home/zou/usr/elkarm/usr/bin/../lib/gcc/arm-linux-gnueabi/4.2.2/soft-float -lgcc \
-Map u-boot.map -o u-boot
arm-linux-objcopy -O srec u-boot u-boot.srec
arm-linux-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
zou@zou-desktop:~/workspace/u-boot-2009.06$

只看该作者 · 2009-8-21 23:49

移植2440 start.s
/*
*  armboot - Startup Code for ARM920 CPU-core
*
*  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
*  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
*  Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/

#include <config.h>
#include <version.h>
#include <status_led.h>

//z2440
#undef CONFIG_DEBUG_LL
#define BWSCON 0x48000000

/* BWSCON */
#define DW8      (0x0)
#define DW16      (0x1)
#define DW32      (0x2)
#define WAIT      (0x1<<2)
#define UBLB      (0x1<<3)

#define B1_BWSCON       (DW32)
#define B2_BWSCON       (DW16)
#define B3_BWSCON       (DW16 + WAIT + UBLB)
#define B4_BWSCON       (DW16)
#define B5_BWSCON       (DW16)
#define B6_BWSCON       (DW32)
#define B7_BWSCON       (DW32)

/* BANK0CON */
#define B0_Tacs      0x0 /*  0clk */
#define B0_Tcos      0x0 /*  0clk */
#define B0_Tacc      0x7 /* 14clk */
#define B0_Tcoh      0x0 /*  0clk */
#define B0_Tah      0x0 /*  0clk */
#define B0_Tacp      0x0
#define B0_PMC      0x0 /* normal */

/* BANK1CON */
#define B1_Tacs      0x0 /*  0clk */
#define B1_Tcos      0x0 /*  0clk */
#define B1_Tacc      0x7 /* 14clk */
#define B1_Tcoh      0x0 /*  0clk */
#define B1_Tah      0x0 /*  0clk */
#define B1_Tacp      0x0
#define B1_PMC      0x0

#define B2_Tacs      0x0
#define B2_Tcos      0x0
#define B2_Tacc      0x7
#define B2_Tcoh      0x0
#define B2_Tah      0x0
#define B2_Tacp      0x0
#define B2_PMC      0x0

#define B3_Tacs      0x0 /*  0clk */
#define B3_Tcos      0x3 /*  4clk */
#define B3_Tacc      0x7 /* 14clk */
#define B3_Tcoh      0x1 /*  1clk */
#define B3_Tah      0x0 /*  0clk */
#define B3_Tacp      0x3    /*  6clk */
#define B3_PMC      0x0 /*  16data */

#define B4_Tacs      0x0 /*  0clk */
#define B4_Tcos      0x0 /*  0clk */
#define B4_Tacc      0x7 /* 14clk */
#define B4_Tcoh      0x0 /*  0clk */
#define B4_Tah      0x0 /*  0clk */
#define B4_Tacp      0x0
#define B4_PMC      0x0 /* normal */

#define B5_Tacs      0x0 /*  0clk */
#define B5_Tcos      0x0 /*  0clk */
#define B5_Tacc      0x7 /* 14clk */
#define B5_Tcoh      0x0 /*  0clk */
#define B5_Tah      0x0 /*  0clk */
#define B5_Tacp      0x0
#define B5_PMC      0x0 /* normal */

#define B6_MT      0x3 /* SDRAM */
#define B6_Trcd           0x1
#define B6_SCAN      0x1 /* 9bit */

#define B7_MT      0x3 /* SDRAM */
#define B7_Trcd      0x1 /* 3clk */
#define B7_SCAN      0x1 /* 9bit */

/* REFRESH parameter */
#define REFEN      0x1 /* Refresh enable */
#define TREFMD      0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp      0x0 /* 2clk */
#define Trc      0x3 /* 7clk */
#define Tchr      0x2 /* 3clk */
#define REFCNT      1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
#define MEM_CTL_BASE 0x48000000
#define vBSWCON  (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
#define vBANKCON0 ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
#define vBANKCON1 ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
#define vBANKCON2 ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
#define vBANKCON3 ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
#define vBANKCON4 ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
#define vBANKCON5 ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
#define vBANKCON6 ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
#define vBANKCON7 ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
#define vREFRESH ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
#define vBANKSIZE 0x32 /* BANKSIZE */
#define vMRSRB6 0x30 /* MRSRB6 */
#define vMRSRB7 0x30 /* MRSRB7 */

/* handy sizes */
#define SZ_1K                         0x00000400
#define SZ_4K                         0x00001000
#define SZ_8K                         0x00002000
#define SZ_16K                         0x00004000
#define SZ_32K                         0x00008000
#define SZ_64K                         0x00010000
#define SZ_128K                      0x00020000
#define SZ_256K                      0x00040000
#define SZ_512K                      0x00080000

#define SZ_1M                         0x00100000
#define SZ_2M                         0x00200000
#define SZ_4M                         0x00400000
#define SZ_8M                         0x00800000
#define SZ_16M                         0x01000000
#define SZ_32M                         0x02000000
#define SZ_64M                         0x04000000
#define SZ_128M                      0x08000000
#define SZ_256M                      0x10000000
#define SZ_512M                      0x20000000

#define SZ_1G                         0x40000000
#define SZ_2G                         0x80000000

#if defined(CONFIG_S3C24A0A)
#define ROM_BASE0             0x00000000    /* base address of rom bank 0 */
#define ROM_BASE1             0x04000000    /* base address of rom bank 1 */
#define DRAM_BASE0             0x10000000    /* base address of dram bank 0 */
#define DRAM_BASE1             0x20000000    /* base address of dram bank 1 */
#elif defined(CONFIG_S3C2440A)
#define ROM_BASE0             0x00000000    /* base address of rom bank 0 */
#define ROM_BASE1             0x08000000    /* base address of rom bank 1 */
#define DRAM_BASE0             0x30000000    /* base address of dram bank 0 */
#endif

#define DRAM_BASE             DRAM_BASE0
#define DRAM_SIZE             SZ_64M

/* total memory required by vivi */
#define UBOOT_SIZE (2*1024*1024)
/* size of vivi binary */
#define MAX_UBOOT_BIN_SIZE (256*1024)
#define MMU_TLB_SIZE (16*1024)
#define HEAP_SIZE (1*1024*1024)
#define STACK_SIZE (512*1024)

/* base address for vivi */
//#define UBOOT_BASE (DRAM_BASE + DRAM_SIZE - UBOOT_SIZE)
#define UBOOT_BASE          TEXT_BASE
#define MMU_TLB_BASE (UBOOT_BASE + MAX_UBOOT_BIN_SIZE)
#define HEAP_BASE (UBOOT_BASE + (512*1024))
#define STACK_BASE (UBOOT_BASE + UBOOT_SIZE - STACK_SIZE)

#define RAM_SIZE (UBOOT_BASE - DRAM_BASE)
#define RAM_BASE DRAM_BASE

//z2440

/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/

.globl _start
_start: b    reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq

_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq

.balignl 16,0xdeadbeef

/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/

_TEXT_BASE:
.word TEXT_BASE

.globl _armboot_start
_armboot_start:
.word _start

/*
* Note: _armboot_end_data and _armboot_end are defined
* by the (board-dependent) linker script.
* _armboot_end_data is the first usable FLASH address after armboot
*/
.globl _armboot_end_data
_armboot_end_data:
.word armboot_end_data
.globl _armboot_end
_armboot_end:
.word armboot_end

/*
* _armboot_real_end is the first usable RAM address behind armboot
* and the various stacks
*/
.globl _armboot_real_end
_armboot_real_end:
.word 0x0badc0de

/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
      .word __bss_start

.globl _bss_end
_bss_end:
      .word _end

/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de

#ifdef CONFIG_S3C2440A_SMDK
@ Processor clock values
#if (CONFIG_SYS_CLK_FREQ ==  12000000)
#define MDIV_405             127
#define PDIV_405             2
#define SDIV_405             1
#define CLKDIVN_148          0x5  /* UCLK = UPLL/2 */
#define vREFRESH_405          992
#define MDIV_96             56
#define PDIV_96             2
#define SDIV_96             1
#define MDIV_48             56
#define PDIV_48             2
#define SDIV_48             2
#define vUPLLCON_NOW_USER    ((MDIV_48 << 12) | (PDIV_48 << 4) | (SDIV_48))
#define vMPLLCON_NOW_USER    ((MDIV_405 << 12) | (PDIV_405 << 4) | (SDIV_405))
#define CLKDIVN_VAL CLKDIVN_148

只看该作者 · 2009-8-21 23:49

2

#else /* SYS_CLK_FREQ == 16.9344Mhz */
#define MDIV_406             184
#define PDIV_406             2
#define SDIV_406             2
#define CLKDIVN_136          0xf /* UCLK = UPLL/2 */
#define vREFRESH_406          992
#define MDIV_96                60
#define PDIV_96                4
#define SDIV_96                1
#define vMPLLCON_NOW_USER    ((MDIV_406 << 12) | (PDIV_406 << 4) | (SDIV_406))
#define vUPLLCON_NOW_USER    ((MDIV_96 << 12) | (PDIV_96 << 4) | (SDIV_96))
#define CLKDIVN_VAL CLKDIVN_136
#endif

#define pWTCON       0x53000000
#define SRCPND 0x4A000000
#define INTMSK       0x4A000008
#define INTSUBMSK    0x4A00001C
#define LOCKTIME 0x4C000000
#define MPLLCON 0x4C000004
#define UPLLCON 0x4C000008
#define CLKCON 0x4C00000C
#define CLKSLOW 0x4C000010
#define CLKDIVN       0x4C000014
#define CAMDIVN 0x4C000018
#define GPFCON 0x56000050
#define GPFDAT 0x56000054
#define GPFUP 0x56000058

/*
* the actual reset code
*/

reset:
/*
   * set the cpu to SVC32 mode
   */
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0

ldr    r0, =pWTCON
mov    r1, #0x0
str    r1, [r0]

/*
   * mask all IRQs by setting all bits in the INTMR - default
   */
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
ldr r2, =0x7ff
ldr r0, =INTSUBMSK
str r2, [r0]

      @ initialize system clocks
ldr r0, =LOCKTIME
ldr    r1, =0xffffff
str    r1, [r0]

      /* FCLK:HCLK:PCLK */
ldr r0, =CAMDIVN
mov r1, #0
str r1, [r0]
      ldr    r0, =CLKDIVN
      ldr    r1, =CLKDIVN_VAL
      str    r1, [r0]

      mrc    p15, 0, r1, c1, c0, 0          @ read ctrl register
      orr    r1, r1, #0xc0000000          @ Asynchronous
      mcr    p15, 0, r1, c1, c0, 0          @ write ctrl register

/* UPLL setup */
      ldr    r0, =UPLLCON
      ldr r1, upll_value_USER
      str    r1, [r0]

nop
nop
nop
nop
nop @ wait until upll has the effect
nop
nop
nop
      /* PLL setup */
ldr    r0, =MPLLCON
ldr r1, mpll_value_USER
str    r1, [r0]

/*
   * we do sys-critical inits only at reboot,
   * not when booting from ram!
   */
#ifdef CONFIG_INIT_CRITICAL
bl cpu_init_crit
#endif

#ifdef CONFIG_PM
@ Check if this is a wake-up from sleep
ldr r1, PMST_ADDR
ldr r0, [r1]
tst r0, #0x2 @ PMST_SMR
bne WakeupStart
#endif

/* Led Configuration */
ldr r0, =GPFCON
ldr r1, =0x55aa
str r1,[r0]

ldr r0, =GPFUP
ldr r1, =0xff
str r1,[r0]

ldr r0, =GPFDAT
ldr r1, =0x70
str r1,[r0]

#ifndef CONFIG_S3C2440A_JTAG_BOOT

#ifdef CONFIG_S3C2440A_NAND_BOOT
bl    copy_myself
#else
relocate:
/*
   * relocate armboot to RAM
   */
adr r0, _start /* r0 <- current position of code */
ldr r2, _armboot_start
ldr r3, _armboot_end
sub r2, r3, r2 /* r2 <- size of armboot */
ldr r1, _TEXT_BASE /* r1 <- destination address */
add r2, r0, r2 /* r2 <- source end address */

/*
   * r0 = source address
   * r1 = target address
   * r2 = source end address
   */
copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
ble copy_loop
#endif
#endif

clear_bss:
      ldr    r0, _bss_start       /* find start of bss segment       */
      add    r0, r0, #4             /* start at first byte of bss    */
      ldr    r1, _bss_end          /* stop here                      */
      mov    r2, #0x00000000       /* clear                         */

clbss_l:str    r2, [r0]             /* clear loop...                   */
      add    r0, r0, #4
      cmp    r0, r1
      bne    clbss_l

/* set up the stack */
ldr r0, _armboot_end
add r0, r0, #CONFIG_STACKSIZE
sub sp, r0, #12 /* leave 3 words for abort-stack */

ldr pc, _start_armboot

_start_armboot: .word start_armboot

.align 4
mpll_value_USER:
      .long vMPLLCON_NOW_USER

upll_value_USER:
      .long vUPLLCON_NOW_USER
#endif

/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/

cpu_init_crit:
/*
   * flush v4 I/D caches
   */
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */

/*
   * disable MMU stuff and caches
   */
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0

/*
   * before relocating, we have to setup RAM timing
   * because memory timing is board-dependend, you will
   * find a memsetup.S in your board directory.
   */
mov ip, lr
bl memsetup
mov lr, ip

mov pc, lr

memsetup:
      @ initialise the static memory

      @ set memory control registers
      mov    r1, #MEM_CTL_BASE
      adrl r2, mem_cfg_val
      add    r3, r1, #52
1:    ldr    r4, [r2], #4
      str    r4, [r1], #4
      cmp    r1, r3
      bne    1b
      mov    pc, lr

只看该作者 · 2009-8-21 23:50

3

/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72

#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52

#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0

#define MODE_SVC 0x13
#define I_BIT    0x80

/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/

.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, _armboot_end
add r2, r2, #CONFIG_STACKSIZE
sub r2, r2, #8
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC

add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp
.endm

.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add    r8, sp, #S_PC
stmdb r8, {sp, lr}^                @ Calling SP, LR
str    lr, [r8, #0]                   @ Save calling PC
mrs    r6, spsr
str    r6, [r8, #4]                   @ Save CPSR
str    r0, [r8, #8]                   @ Save OLD_R0
mov r0, sp
.endm

.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm

.macro get_bad_stack
ldr r13, _armboot_end @ setup our mode stack
add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
sub r13, r13, #8

str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str    lr, [r13, #4]

mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13
mov lr, pc
movs pc, lr
.endm

.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm

.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm

/*
* exception handlers
*/
.align  5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction

.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt

.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort

.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort

.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used

.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs

.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs

#ifdef CONFIG_PM
WakeupStart:
@ Clear sleep reset bit
ldr r0, PMST_ADDR
mov r1, #(1<<1) @ PMST_SMR
str r1, [r0]

@ Release the SDRAM signal protections
ldr r0, PMCTL1_ADDR
ldr r1, [r0]
bic r1, r1, #((1<<17)|(1<<18)|(1<<19))  @ (SCLKE | SCLK1 | SCLK0)
str r1, [r0]

@ Go...
ldr r0, PMSR0_ADDR  @ read a return address
ldr r1, [r0]
mov pc, r1
nop
nop
1:  b 1b    @ infinite loop
#endif

.align 5
.globl reset_cpu
reset_cpu:
#ifdef CONFIG_S3C2400
bl disable_interrupts
# ifdef CONFIG_TRAB
bl disable_vfd
# endif
ldr r1, _rWTCON
ldr r2, _rWTCNT
/* Disable watchdog */
mov r3, #0x0000
str r3, [r1]
/* Initialize watchdog timer count register */
mov r3, #0x0001
str r3, [r2]
/* Enable watchdog timer; assert reset at timer timeout */
mov r3, #0x0021
str r3, [r1]
_loop_forever:
b _loop_forever
_rWTCON:
.word 0x15300000
_rWTCNT:
.word 0x15300008
#else /* ! CONFIG_S3C2400 */
mov    ip, #0
mcr    p15, 0, ip, c7, c7, 0          @ invalidate cache
mcr    p15, 0, ip, c8, c7, 0          @ flush TLB (v4)
mrc    p15, 0, ip, c1, c0, 0          @ get ctrl register
bic    ip, ip, #0x000f                @ ............wcam
bic    ip, ip, #0x2100                @ ..v....s........
mcr    p15, 0, ip, c1, c0, 0          @ ctrl register
mov    pc, r0
#endif /* CONFIG_S3C2400 */

#ifndef CONFIG_S3C2440A_JTAG_BOOT

#ifdef CONFIG_S3C2440A_NAND_BOOT
copy_myself:

ldr r0, =GPFDAT
ldr r1, =0x10
str r1,[r0]

      mov    r10, lr       @ save return address

      @ get ready to call C functions
      ldr    sp, uboot_stack_pointer @ setup stack pointer
      mov    fp, #0                @ no previous frame, so fp=0

      bl    copy_uboot_to_ram

      tst    r0, #0x0
      bne    copy_myself_failed

ldr r0, =GPFDAT
ldr r1, =0x20
str r1,[r0]

      mov    r0, #0
      ldr    r1, uboot_ram_base_addr
      mov    r2, #0x400    @ compare first 4-K bytes
1001: ldr    r3, [r0], #4
      ldr    r4, [r1], #4
      teq    r3, r4
      bne    1002f          @ not matched
      subs r2, r2, #4
      beq    1003f
      b    1001b

1002:
ldr r0, =GPFDAT
ldr r1, =0x30
str r1,[r0]

1:    b    1b

1003:

ldr r0, =GPFDAT
ldr r1, =0x40
str r1,[r0]

      @ jump to ram
      ldr    r0, uboot_ram_base_addr
      add    pc, r10, r0    /* fake ^^;  return here. */

copy_myself_failed:
1:    b    1b

#endif
#endif

.ltorg

.align 2

@ addresses
uboot_stack_pointer: .long (STACK_BASE + STACK_SIZE - 4)
uboot_ram_base_addr: .long UBOOT_BASE

.align 4
mem_cfg_val:
.long vBSWCON
      .long vBANKCON0
      .long vBANKCON1
      .long vBANKCON2
      .long vBANKCON3
      .long vBANKCON4
      .long vBANKCON5
      .long vBANKCON6
      .long vBANKCON7
      .long vREFRESH
      .long vBANKSIZE
      .long vMRSRB6
      .long vMRSRB7
#ifdef CONFIG_PM
.align 4
PMCTL1_ADDR:
.long 0x56000080
PMST_ADDR:
.long 0x560000B4
PMSR0_ADDR:
.long 0x560000B8
#endif

只看该作者 · 2009-8-22 00:17

-Map u-boot.map -o u-boot
cpu/arm920t/s3c24x0/libs3c24x0.a(interrupts.o): In function `reset_cpu':
/home/zou/workspace/u-boot-2009.06/cpu/arm920t/s3c24x0/interrupts.c:206: multiple definition of `reset_cpu'
cpu/arm920t/start.o:/home/zou/workspace/u-boot-2009.06/cpu/arm920t/start.S:738: first defined here
cpu/arm920t/start.o: In function `_start':
(.text+0x0): undefined reference to `reset'
cpu/arm920t/start.o: In function `_armboot_end_data':
(.text+0x48): undefined reference to `armboot_end_data'
cpu/arm920t/start.o: In function `_armboot_end':
(.text+0x4c): undefined reference to `armboot_end'
make: *** [u-boot] 错误 1

只看该作者 · 2009-8-22 13:42

好文转载
http://blog.**/xiong_gang_whut/240009/Message.aspx

只看该作者 · 2009-8-25 18:52

rpm -ivh VMwareTools-7.8.5-156735.i386.rpm

只看该作者 · 2013-10-14 09:47

itelectron 发表于 2009-8-19 22:58
smdk2440.c:29:21: error: s3c2440.h: No such file or directory
smdk2440.c: In function 'board_init':
...

make[1]: Entering directory `/test/u-boot-2010.06/board/samsung/smdk2440'
flash.c:75:2: error: #error "Unknown flash configured"
make[1]: *** No rule to make target `.depend', needed by `libsmdk2440.a'. Stop.
make[1]: Leaving directory `/test/u-boot-2010.06/board/samsung/smdk2440'
make: *** [board/samsung/smdk2440/libsmdk2440.a] Error 2
请教你这个问题怎么解决的呢