TIVA注意使能模块时钟时需要加个6cycle以上的延时

很多用户在使用TI M4的时候，会忽略一个细节，在使能外设模块时钟，直接去操作此模块，会导致进入FaultIsr中断服务入口，导致无法调试。



在函数注释说明有个NOTE，大家可能没有注意到。如下：



//! \note It takes five clock cycles after the write to enable a peripheral

//! before the the peripheral is actually enabled. During this time, attempts

//! to access the peripheral result in a bus fault. Care should be taken

//! to ensure that the peripheral is not accessed during this brief time

//! period.



extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);



//*****************************************************************************

//

//! Enables a peripheral.

//!

//! \param ui32Peripheral is the peripheral to enable.

//!

//! This function enables a peripheral. At power-up, all peripherals are

//! disabled; they must be enabled in order to operate or respond to register

//! reads/writes.

//!

//! The \e ui32Peripheral parameter must be only one of the following values:

//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,

//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,

//! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,

//! \b SYSCTL_PERIPH_EPI0,

//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,

//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,

//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,

//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,

//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,

//! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,

//! \b SYSCTL_PERIPH_HIBERNATE,

//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,

//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,

//! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,

//! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,

//! \b SYSCTL_PERIPH_ONEWIRE0,

//! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,

//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,

//! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,

//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,

//! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,

//! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,

//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,

//! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,

//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,

//! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,

//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,

//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5

//!

//! \note It takes five clock cycles after the write to enable a peripheral

//! before the the peripheral is actually enabled. During this time, attempts

//! to access the peripheral result in a bus fault. Care should be taken

//! to ensure that the peripheral is not accessed during this brief time

//! period.



//!

//! \return None.

//

//*****************************************************************************

void

SysCtlPeripheralEnable(uint32_t ui32Peripheral)

{

//

// Check the arguments.

//

ASSERT(_SysCtlPeripheralValid(ui32Peripheral));



//

// Enable this peripheral.

//

HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),

ui32Peripheral & 0xff) = 1;

}