always@(posedge clk_1Hz or negedge rst )
begin
if(!rst) current_state<=2'b00;
else current_state<=next_state;
end
always@(current_state)
case (current_state)
s0: next_state<=s1;
s1: next_state<=s2;
s2: next_state<=s3;
s3: next_state<=s0;
default : next_state<=s0;
endcase
always@(current_state )
case (current_state)
s0:led<=2'b00;
s1:led<=2'b01;
s2:led<=2'b10;
s3:led<=2'b11;
default : led<=2'b00;
endcase |
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