/*---------------------------------------------------------------------------------------------------------*/
/* PLLCON constant definitions. PLL = FIN * NF / NR / NO */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PLLCON_PLL_SRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN < 24MHz */
#define CLK_PLLCON_PLL_SRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN < 24MHz */
#define CLK_PLLCON_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 15MHz */
#define CLK_PLLCON_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.) */
#define CLK_PLLCON_NO_1 0x0000UL /*!< For output divider is 1 */
#define CLK_PLLCON_NO_2 0x4000UL /*!< For output divider is 2 */
#define CLK_PLLCON_NO_4 0xC000UL /*!< For output divider is 4 */
#define CLK_PLLCON_50MHz_HXT (CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR(3) | CLK_PLLCON_NF( 25) | CLK_PLLCON_NO_2) /*!< Predefined PLLCON setting for 50MHz PLL output with 12MHz X'tal */
#define CLK_PLLCON_50MHz_HIRC (CLK_PLLCON_PLL_SRC_HIRC | CLK_PLLCON_NR(13) | CLK_PLLCON_NF( 59) | CLK_PLLCON_NO_2) /*!< Predefined PLLCON setting for 50.1918MHz PLL output with 22.1184MHz IRC */
/*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions.
//////////////////////////////////////////////////////////////
#if USER_PLL_ClOCK == USER
#if USER_SYSTEM_CLK == OSCL
// 22.1184M Oscl To 50M
User_PLLCON->FB_DV = 0x39; // PLL反馈分频控制
User_PLLCON->IN_DV = 0x0B; // PLL输入分频控制
User_PLLCON->OUT_DV = 0x01; // PLL输出分频控制
User_PLLCON->PD = 0; // 0: PLL正常模式 1: = PLL 掉电模式(默认)
User_PLLCON->BP = 0; // 0: PLL 正常模式 (默认) 1: = PLL 时钟输出与时钟输入相同
User_PLLCON->OE = 0; // 0: 使能 PLL FOUT 1: PLL FOUT 固定为低
User_PLLCON->PLL_SRC = 1; // 0: PLL时钟源为外部高速晶振HXT（ 4~24MHz）1: PLL 时钟源为22.1184 MHz 振荡器HIRC
while (!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk)); // 检测 PLL 是否就绪
#elif USER_SYSTEM_CLK == XTAL
// 12M Xtal To 50M
User_PLLCON->FB_DV = 0x17; // PLL反馈分频控制
User_PLLCON->IN_DV = 0x01; // PLL输入分频控制
User_PLLCON->OUT_DV = 0x01; // PLL输出分频控制
User_PLLCON->PD = 0; // 0: PLL正常模式 1: = PLL 掉电模式(默认)
User_PLLCON->BP = 0; // 0: PLL 正常模式 (默认) 1: = PLL 时钟输出与时钟输入相同
User_PLLCON->OE = 0; // 0: 使能 PLL FOUT 1: = PLL FOUT 固定为低
User_PLLCON->PLL_SRC = 0; // 0: PLL时钟源为外部高速晶振HXT（ 4~24MHz）1: PLL 时钟源为22.1184 MHz 振荡器HIRC
#endif
这些PLLCON这样写的功能是设置频率吗？ |
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