M451例程之PWM的寄存器讲解

typedef struct

{





/**

 * [url=home.php?mod=space&uid=176933]@VAR[/url] PWM_T::CTL0

 * Offset: 0x00  PWM Control Register 0

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[5:0]   |CTRLDn    |Center Re-Load

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period.

 * |        |          |CMPDAT will load to CMPBUF at the center point of a period.

 * |[13:8]  |WINLDENn  |Window Load Enable

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |0 = PERIOD will load to PBUF at the end point of each period.

 * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.

 * |        |          |1 = PERIOD will load to PBUF at the end point of each period.

 * |        |          |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.

 * |        |          |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.

 * |[21:16] |IMMLDENn  |Immediately Load Enable

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |0 = PERIOD will load to PBUF at the end point of each period.

 * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.

 * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.

 * |        |          |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.

 * |[24]    |GROUPEN   |Group Function Enable

 * |        |          |0 = The output waveform of each PWM channel are independent.

 * |        |          |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.

 * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)

 * |        |          |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.

 * |        |          |0 = ICE debug mode counter halt disable.

 * |        |          |1 = ICE debug mode counter halt enable.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)

 * |        |          |0 = ICE debug mode acknowledgement effects PWM output.

 * |        |          |PWM pin will be forced as tri-state while ICE debug mode acknowledged.

 * |        |          |1 = ICE debug mode acknowledgement disabled.

 * |        |          |PWM pin will keep output no matter ICE debug mode acknowledged or not.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * @var PWM_T::CTL1

 * Offset: 0x04  PWM Control Register 1

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |CNTTYPEn  |PWM Counter Behavior Type

 * |        |          |Each bit n controls corresponding PWM channel n.

 * |        |          |00 = Up counter type (supports in capture mode).

 * |        |          |01 = Down count type (supports in capture mode).

 * |        |          |10 = Up-down counter type.

 * |        |          |11 = Reserved.

 * |[21:16] |CNTMODEn  |PWM Counter Mode

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |0 = Auto-reload mode.

 * |        |          |1 = One-shot mode.

 * |[26:24] |OUTMODEn  |PWM Output Mode

 * |        |          |Each bit n controls the

 * |        |          |output mode of

 * |        |          |corresponding PWM channel n.

 * |        |          |0 = PWM independent mode.

 * |        |          |1 = PWM complementary mode.

 * |        |          |Note: When operating in group function, these bits must all set to the same mode.

 * @var PWM_T::SYNC

 * Offset: 0x08  PWM Synchronization Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[2:0]   |PHSENn    |SYNC Phase Enable

 * |        |          |Each bit n controls corresponding PWM channel n.

 * |        |          |0 = PWM counter disable to load PHS value.

 * |        |          |1 = PWM counter enable to load PHS value.

 * |[13:8]  |SINSRCn   |PWM_SYNC_IN Source Selection

 * |        |          |Each bit n controls corresponding PWM channel n.

 * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.

 * |        |          |01 = Counter equal to 0.

 * |        |          |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.

 * |        |          |11 = SYNC_OUT will not be generated.

 * |[16]    |SNFLTEN   |PWM_SYNC_IN Noise Filter Enable

 * |        |          |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.

 * |        |          |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.

 * |[19:17] |SFLTCSEL  |SYNC Edge Detector Filter Clock Selection

 * |        |          |000 = Filter clock = HCLK.

 * |        |          |001 = Filter clock = HCLK/2.

 * |        |          |010 = Filter clock = HCLK/4.

 * |        |          |011 = Filter clock = HCLK/8.

 * |        |          |100 = Filter clock = HCLK/16.

 * |        |          |101 = Filter clock = HCLK/32.

 * |        |          |110 = Filter clock = HCLK/64.

 * |        |          |111 = Filter clock = HCLK/128.

 * |[22:20] |SFLTCNT   |SYNC Edge Detector Filter Count

 * |        |          |The register bits control the counter number of edge detector.

 * |[23]    |SINPINV   |SYNC Input Pin Inverse

 * |        |          |0 = The state of pin SYNC is passed to the negative edge detector.

 * |        |          |1 = The inverted state of pin SYNC is passed to the negative edge detector.

 * |[26:24] |PHSDIRn   |PWM Phase Direction Control

 * |        |          |Each bit n controls corresponding PWM channel n.

 * |        |          |0 = Control PWM counter count decrement after synchronizing.

 * |        |          |1 = Control PWM counter count increment after synchronizing.

 * @var PWM_T::SWSYNC

 * Offset: 0x0C  PWM Software Control Synchronization Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[2:0]   |SWSYNCn   |Software SYNC Function

 * |        |          |Each bit n controls corresponding PWM channel n.

 * |        |          |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.

 * @var PWM_T::CLKSRC

 * Offset: 0x10  PWM Clock Source Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[2:0]   |ECLKSRC0  |PWM_CH01 External Clock Source Select

 * |        |          |000 = PWMx_CLK, x denotes 0 or 1.

 * |        |          |001 = TIMER0 overflow.

 * |        |          |010 = TIMER1 overflow.

 * |        |          |011 = TIMER2 overflow.

 * |        |          |100 = TIMER3 overflow.

 * |        |          |Others = Reserved.

 * |[10:8]  |ECLKSRC2  |PWM_CH23 External Clock Source Select

 * |        |          |000 = PWMx_CLK, x denotes 0 or 1.

 * |        |          |001 = TIMER0 overflow.

 * |        |          |010 = TIMER1 overflow.

 * |        |          |011 = TIMER2 overflow.

 * |        |          |100 = TIMER3 overflow.

 * |        |          |Others = Reserved.

 * |[18:16] |ECLKSRC4  |PWM_CH45 External Clock Source Select

 * |        |          |000 = PWMx_CLK, x denotes 0 or 1.

 * |        |          |001 = TIMER0 overflow.

 * |        |          |010 = TIMER1 overflow.

 * |        |          |011 = TIMER2 overflow.

 * |        |          |100 = TIMER3 overflow.

 * |        |          |Others = Reserved.

 * @var PWM_T::CLKPSC0_1

 * Offset: 0x14  PWM Clock Pre-scale Register 0

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-Scale

 * |        |          |The clock of PWM counter is decided by clock prescaler.

 * |        |          |Each PWM pair share one PWM counter clock prescaler.

 * |        |          |The clock of PWM counter is divided by (CLKPSC+ 1).

 * @var PWM_T::CLKPSC2_3

 * Offset: 0x18  PWM Clock Pre-scale Register 2

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-Scale

 * |        |          |The clock of PWM counter is decided by clock prescaler.

 * |        |          |Each PWM pair share one PWM counter clock prescaler.

 * |        |          |The clock of PWM counter is divided by (CLKPSC+ 1).

 * @var PWM_T::CLKPSC4_5

 * Offset: 0x1C  PWM Clock Pre-scale Register 4

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-Scale

 * |        |          |The clock of PWM counter is decided by clock prescaler.

 * |        |          |Each PWM pair share one PWM counter clock prescaler.

 * |        |          |The clock of PWM counter is divided by (CLKPSC+ 1).

 * @var PWM_T::CNTEN

 * Offset: 0x20  PWM Counter Enable Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[5:0]   |CNTENn    |PWM Counter Enable

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |0 = PWM Counter and clock prescaler Stop Running.

 * |        |          |1 = PWM Counter and clock prescaler Start Running.

 * @var PWM_T::CNTCLR

 * Offset: 0x24  PWM Clear Counter Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[5:0]   |CNTCLRn   |Clear PWM Counter Control Bit

 * |        |          |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.

 * |        |          |0 = No effect.

 * |        |          |1 = Clear 16-bit PWM counter to 0000H.

 * @var PWM_T::LOAD

 * Offset: 0x28  PWM Load Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[5:0]   |LOADn     |Re-Load PWM Comparator Register (CMPDAT) Control Bit

 * |        |          |This bit is software write, hardware clear when current PWM period end.

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |Write Operation:

 * |        |          |0 = No effect.

 * |        |          |1 = Set load window of window loading mode.

 * |        |          |Read Operation:

 * |        |          |0 = No load window is set.

 * |        |          |1 = Load window is set.

 * |        |          |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.

 * @var PWM_T::PERIOD

 * Offset: 0x30~0x44  PWM Period Register 0~5

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[15:0]  |PERIOD    |PWM Period Register

 * |        |          |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.

 * |        |          |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.

 * |        |          |PWM period time = (PERIOD+1) * PWM_CLK period.

 * |        |          |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.

 * |        |          |PWM period time = 2 * PERIOD * PWM_CLK period.

 * @var PWM_T::CMPDAT

 * Offset: 0x50~0x64  PWM Comparator Register 0~5

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[15:0]  |CMP       |PWM Comparator Register

 * |        |          |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.

 * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.

 * |        |          |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.

 * @var PWM_T::DTCTL0_1

 * Offset: 0x70  PWM Dead-Time Control Register 0

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |DTCNT     |Dead-Time Counter (Write Protect)

 * |        |          |The dead-time can be calculated from the following formula:

 * |        |          |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[16]    |DTEN      |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)

 * |        |          |Dead-time insertion is only active when this pair of complementary PWM is enabled.

 * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.

 * |        |          |0 = Dead-time insertion Disabled on the pin pair.

 * |        |          |1 = Dead-time insertion Enabled on the pin pair.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[24]    |DTCKSEL   |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)

 * |        |          |0 = Dead-time clock source from PWM_CLK.

 * |        |          |1 = Dead-time clock source from prescaler output.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * @var PWM_T::DTCTL2_3

 * Offset: 0x74  PWM Dead-Time Control Register 2

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |DTCNT     |Dead-Time Counter (Write Protect)

 * |        |          |The dead-time can be calculated from the following formula:

 * |        |          |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[16]    |DTEN      |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)

 * |        |          |Dead-time insertion is only active when this pair of complementary PWM is enabled.

 * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.

 * |        |          |0 = Dead-time insertion Disabled on the pin pair.

 * |        |          |1 = Dead-time insertion Enabled on the pin pair.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[24]    |DTCKSEL   |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)

 * |        |          |0 = Dead-time clock source from PWM_CLK.

 * |        |          |1 = Dead-time clock source from prescaler output.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * @var PWM_T::DTCTL4_5

 * Offset: 0x78  PWM Dead-Time Control Register 4

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |DTCNT     |Dead-Time Counter (Write Protect)

 * |        |          |The dead-time can be calculated from the following formula:

 * |        |          |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[16]    |DTEN      |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)

 * |        |          |Dead-time insertion is only active when this pair of complementary PWM is enabled.

 * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.

 * |        |          |0 = Dead-time insertion Disabled on the pin pair.

 * |        |          |1 = Dead-time insertion Enabled on the pin pair.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * |[24]    |DTCKSEL   |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)

 * |        |          |0 = Dead-time clock source from PWM_CLK.

 * |        |          |1 = Dead-time clock source from prescaler output.

 * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

 * @var PWM_T::PHS0_1

 * Offset: 0x80  PWM Counter Phase Register 0

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[15:0]  |PHS       |PWM Synchronous Start Phase Bits

 * |        |          |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.

 * @var PWM_T::PHS2_3

 * Offset: 0x84  PWM Counter Phase Register 2

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[15:0]  |PHS       |PWM Synchronous Start Phase Bits

 * |        |          |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.

 * @var PWM_T::PHS4_5

 * Offset: 0x88  PWM Counter Phase Register 4

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[15:0]  |PHS       |PWM Synchronous Start Phase Bits

 * |        |          |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.

 * @var PWM_T::CNT

 * Offset: 0x90~0xA4  PWM Counter Register 0~5

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[15:0]  |CNT       |PWM Data Register (Read Only)

 * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.

 * |[16]    |DIRF      |PWM Direction Indicator Flag (Read Only)

 * |        |          |0 = Counter is Down count.

 * |        |          |1 = Counter is UP count.

 * @var PWM_T::WGCTL0

 * Offset: 0xB0  PWM Generation Register 0

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |ZPCTLn    |PWM Zero Point Control

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |00 = Do nothing.

 * |        |          |01 = PWM zero point output Low.

 * |        |          |10 = PWM zero point output High.

 * |        |          |11 = PWM zero point output Toggle.

 * |        |          |PWM can control output level when PWM counter count to zero.

 * |[27:16] |PRDPCTLn  |PWM Period (Center) Point Control

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |00 = Do nothing.

 * |        |          |01 = PWM period (center) point output Low.

 * |        |          |10 = PWM period (center) point output High.

 * |        |          |11 = PWM period (center) point output Toggle.

 * |        |          |PWM can control output level when PWM counter count to (PERIODn+1).

 * |        |          |Note: This bit is center point control when PWM counter operating in up-down counter type.

 * @var PWM_T::WGCTL1

 * Offset: 0xB4  PWM Generation Register 1

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[11:0]  |CMPUCTLn  |PWM Compare Up Point Control

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |00 = Do nothing.

 * |        |          |01 = PWM compare up point output Low.

 * |        |          |10 = PWM compare up point output High.

 * |        |          |11 = PWM compare up point output Toggle.

 * |        |          |PWM can control output level when PWM counter up count to CMPDAT.

 * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.

 * |[27:16] |CMPDCTLn  |PWM Compare Down Point Control

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |00 = Do nothing.

 * |        |          |01 = PWM compare down point output Low.

 * |        |          |10 = PWM compare down point output High.

 * |        |          |11 = PWM compare down point output Toggle.

 * |        |          |PWM can control output level when PWM counter down count to CMPDAT.

 * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.

 * @var PWM_T::MSKEN

 * Offset: 0xB8  PWM Mask Enable Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[5:0]   |MSKENn    |PWM Mask Enable

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |The PWM output signal will be masked when this bit is enabled.

 * |        |          |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.

 * |        |          |0 = PWM output signal is non-masked.

 * |        |          |1 = PWM output signal is masked and output MSKDATn data.

 * @var PWM_T::MSK

 * Offset: 0xBC  PWM Mask Data Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[5:0]   |MSKDATn   |PWM Mask Data Bit

 * |        |          |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.

 * |        |          |Each bit n controls the corresponding PWM channel n.

 * |        |          |0 = Output logic low to PWMn.

 * |        |          |1 = Output logic high to PWMn.

 * @var PWM_T::BNF

 * Offset: 0xC0  PWM Brake Noise Filter Register

 * ---------------------------------------------------------------------------------------------------

 * |Bits    |Field     |Descriptions

 * | :----: | :----:   | :---- |

 * |[0]     |BRK0NFEN  |PWM Brake 0 Noise Filter Enable

 * |        |          |0 = Noise filter of PWM Brake 0 Disabled.

 * |        |          |1 = Noise filter of PWM Brake 0 Enabled.

 * |[3:1]   |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection

 * |        |          |000 = Filter clock = HCLK.

 * |        |          |001 = Filter clock = HCLK/2.

 * |        |          |010 = Filter clock = HCLK/4.

 * |        |          |011 = Filter clock = HCLK/8.

 * |        |          |100 = Filter clock = HCLK/16.

 * |        |          |101 = Filter clock = HCLK/32.

 * |        |          |110 = Filter clock = HCLK/64.

 * |        |          |111 = Filter clock = HCLK/128.

* |[6:4]   |BRK0FCNT  |Brake 0 Edge Detector Filter Count

* |        |          |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.

* |[7]     |BRK0PINV  |Brake 0 Pin Inverse

* |        |          |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.

* |        |          |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.

* |[8]     |BRK1NFEN  |PWM Brake 1 Noise Filter Enable

* |        |          |0 = Noise filter of PWM Brake 1 Disabled.

* |        |          |1 = Noise filter of PWM Brake 1 Enabled.

* |[11:9]  |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection

* |        |          |000 = Filter clock = HCLK.

* |        |          |001 = Filter clock = HCLK/2.

* |        |          |010 = Filter clock = HCLK/4.

* |        |          |011 = Filter clock = HCLK/8.

* |        |          |100 = Filter clock = HCLK/16.

* |        |          |101 = Filter clock = HCLK/32.

* |        |          |110 = Filter clock = HCLK/64.

* |        |          |111 = Filter clock = HCLK/128.

* |[14:12] |BRK1FCNT  |Brake 1 Edge Detector Filter Count

* |        |          |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.

* |[15]    |BRK1PINV  |Brake 1 Pin Inverse

* |        |          |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.

* |        |          |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.

* |[16]    |BK0SRC    |Brake 0 Pin Source Select (M45xD/M45xC Only)

* |        |          |For PWM0 setting:

* |        |          |0 = Brake 0 pin source come from PWM0_BRAKE0.

* |        |          |1 = Brake 0 pin source come from PWM1_BRAKE0.

* |        |          |For PWM1 setting:

* |        |          |0 = Brake 0 pin source come from PWM1_BRAKE0.

* |        |          |1 = Brake 0 pin source come from PWM0_BRAKE0.

* |[24]    |BK1SRC    |Brake 1 Pin Source Select (M45xD/M45xC Only)

* |        |          |For PWM0 setting:

* |        |          |0 = Brake 1 pin source come from PWM0_BRAKE1.

* |        |          |1 = Brake 1 pin source come from PWM1_BRAKE1.

* |        |          |For PWM1 setting:

* |        |          |0 = Brake 1 pin source come from PWM1_BRAKE1.

* |        |          |1 = Brake 1 pin source come from PWM0_BRAKE1.

* @var PWM_T::FAILBRK

* Offset: 0xC4  PWM System Fail Brake Control Register

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[0]     |CSSBRKEN  |Clock Security System Detection Trigger PWM Brake Function 0 Enable

* |        |          |0 = Brake Function triggered by CSS detection Disabled.

* |        |          |1 = Brake Function triggered by CSS detection Enabled.

* |[1]     |BODBRKEN  |Brown-Out Detection Trigger PWM Brake Function 0 Enable

* |        |          |0 = Brake Function triggered by BOD Disabled.

* |        |          |1 = Brake Function triggered by BOD Enabled.

* |[2]     |RAMBRKEN  |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable

* |        |          |0 = Brake Function triggered by SRAM parity error detection Disabled.

* |        |          |1 = Brake Function triggered by SRAM parity error detection Enabled.

* |[3]     |CORBRKEN  |Core Lockup Detection Trigger PWM Brake Function 0 Enable

* |        |          |0 = Brake Function triggered by Core lockup detection Disabled.

* |        |          |1 = Brake Function triggered by Core lockup detection Enabled.

* @var PWM_T::BRKCTL0_1

* Offset: 0xC8  PWM Brake Edge Detect Control Register 0

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP0_O as edge-detect brake source Disabled.

* |        |          |1 = ACMP0_O as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP1_O as edge-detect brake source Disabled.

* |        |          |1 = ACMP1_O as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[4]     |BRKP0EEN  |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = BKP0 pin as edge-detect brake source Disabled.

* |        |          |1 = BKP0 pin as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[5]     |BRKP1EEN  |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = BKP1 pin as edge-detect brake source Disabled.

* |        |          |1 = BKP1 pin as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[7]     |SYSEBEN   |Enable System Fail As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = System Fail condition as edge-detect brake source Disabled.

* |        |          |1 = System Fail condition as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP0_O as level-detect brake source Disabled.

* |        |          |1 = ACMP0_O as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP1_O as level-detect brake source Disabled.

* |        |          |1 = ACMP1_O as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)

* |        |          |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.

* |        |          |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)

* |        |          |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.

* |        |          |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[15]    |SYSLBEN   |Enable System Fail As Level-Detect Brake Source (Write Protect)

* |        |          |0 = System Fail condition as level-detect brake source Disabled.

* |        |          |1 = System Fail condition as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[17:16] |BRKAEVEN  |PWM Brake Action Select For Even Channel (Write Protect)

* |        |          |00 = PWM even channel level-detect brake function not affect channel output.

* |        |          |01 = PWM even channel output tri-state when level-detect brake happened.

* |        |          |10 = PWM even channel output low level when level-detect brake happened.

* |        |          |11 = PWM even channel output high level when level-detect brake happened.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[19:18] |BRKAODD   |PWM Brake Action Select For Odd Channel (Write Protect)

* |        |          |00 = PWM odd channel level-detect brake function not affect channel output.

* |        |          |01 = PWM odd channel output tri-state when level-detect brake happened.

* |        |          |10 = PWM odd channel output low level when level-detect brake happened.

* |        |          |11 = PWM odd channel output high level when level-detect brake happened.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* @var PWM_T::BRKCTL2_3

* Offset: 0xCC  PWM Brake Edge Detect Control Register 2

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP0_O as edge-detect brake source Disabled.

* |        |          |1 = ACMP0_O as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP1_O as edge-detect brake source Disabled.

* |        |          |1 = ACMP1_O as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[4]     |BRKP0EEN  |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = BKP0 pin as edge-detect brake source Disabled.

* |        |          |1 = BKP0 pin as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[5]     |BRKP1EEN  |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = BKP1 pin as edge-detect brake source Disabled.

* |        |          |1 = BKP1 pin as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[7]     |SYSEBEN   |Enable System Fail As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = System Fail condition as edge-detect brake source Disabled.

* |        |          |1 = System Fail condition as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP0_O as level-detect brake source Disabled.

* |        |          |1 = ACMP0_O as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP1_O as level-detect brake source Disabled.

* |        |          |1 = ACMP1_O as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)

* |        |          |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.

* |        |          |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)

* |        |          |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.

* |        |          |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[15]    |SYSLBEN   |Enable System Fail As Level-Detect Brake Source (Write Protect)

* |        |          |0 = System Fail condition as level-detect brake source Disabled.

* |        |          |1 = System Fail condition as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[17:16] |BRKAEVEN  |PWM Brake Action Select For Even Channel (Write Protect)

* |        |          |00 = PWM even channel level-detect brake function not affect channel output.

* |        |          |01 = PWM even channel output tri-state when level-detect brake happened.

* |        |          |10 = PWM even channel output low level when level-detect brake happened.

* |        |          |11 = PWM even channel output high level when level-detect brake happened.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[19:18] |BRKAODD   |PWM Brake Action Select For Odd Channel (Write Protect)

* |        |          |00 = PWM odd channel level-detect brake function not affect channel output.

* |        |          |01 = PWM odd channel output tri-state when level-detect brake happened.

* |        |          |10 = PWM odd channel output low level when level-detect brake happened.

* |        |          |11 = PWM odd channel output high level when level-detect brake happened.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* @var PWM_T::BRKCTL4_5

* Offset: 0xD0  PWM Brake Edge Detect Control Register 4

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP0_O as edge-detect brake source Disabled.

* |        |          |1 = ACMP0_O as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP1_O as edge-detect brake source Disabled.

* |        |          |1 = ACMP1_O as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[4]     |BRKP0EEN  |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = BKP0 pin as edge-detect brake source Disabled.

* |        |          |1 = BKP0 pin as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[5]     |BRKP1EEN  |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = BKP1 pin as edge-detect brake source Disabled.

* |        |          |1 = BKP1 pin as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[7]     |SYSEBEN   |Enable System Fail As Edge-Detect Brake Source (Write Protect)

* |        |          |0 = System Fail condition as edge-detect brake source Disabled.

* |        |          |1 = System Fail condition as edge-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP0_O as level-detect brake source Disabled.

* |        |          |1 = ACMP0_O as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)

* |        |          |0 = ACMP1_O as level-detect brake source Disabled.

* |        |          |1 = ACMP1_O as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)

* |        |          |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.

* |        |          |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)

* |        |          |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.

* |        |          |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[15]    |SYSLBEN   |Enable System Fail As Level-Detect Brake Source (Write Protect)

* |        |          |0 = System Fail condition as level-detect brake source Disabled.

* |        |          |1 = System Fail condition as level-detect brake source Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[17:16] |BRKAEVEN  |PWM Brake Action Select For Even Channel (Write Protect)

* |        |          |00 = PWM even channel level-detect brake function not affect channel output.

* |        |          |01 = PWM even channel output tri-state when level-detect brake happened.

* |        |          |10 = PWM even channel output low level when level-detect brake happened.

* |        |          |11 = PWM even channel output high level when level-detect brake happened.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[19:18] |BRKAODD   |PWM Brake Action Select For Odd Channel (Write Protect)

* |        |          |00 = PWM odd channel level-detect brake function not affect channel output.

* |        |          |01 = PWM odd channel output tri-state when level-detect brake happened.

* |        |          |10 = PWM odd channel output low level when level-detect brake happened.

* |        |          |11 = PWM odd channel output high level when level-detect brake happened.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* @var PWM_T::POLCTL

* Offset: 0xD4  PWM Pin Polar Inverse Register

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[5:0]   |PINVn     |PWM PIN Polar Inverse Control

* |        |          |The register controls polarity state of PWM output.

* |        |          |Each bit n controls the corresponding PWM channel n.

* |        |          |0 = PWM output polar inverse Disabled.

* |        |          |1 = PWM output polar inverse Enabled.

* @var PWM_T::POEN

* Offset: 0xD8  PWM Output Enable Register

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[5:0]   |POENn     |PWM Pin Output Enable

* |        |          |Each bit n controls the corresponding PWM channel n.

* |        |          |0 = PWM pin at tri-state.

* |        |          |1 = PWM pin in output mode.

* @var PWM_T::SWBRK

* Offset: 0xDC  PWM Software Brake Control Register

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[2:0]   |BRKETRGn  |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)

* |        |          |Each bit n controls the corresponding PWM pair n.

* |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[10:8]  |BRKLTRGn  |PWM Level Brake Software Trigger (Write Only) (Write Protect)

* |        |          |Each bit n controls the corresponding PWM pair n.

* |        |          |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* @var PWM_T::INTEN0

* Offset: 0xE0  PWM Interrupt Enable Register 0

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[5:0]   |ZIENn     |PWM Zero Point Interrupt Enable

* |        |          |Each bit n controls the corresponding PWM channel n.

* |        |          |0 = Zero point interrupt Disabled.

* |        |          |1 = Zero point interrupt Enabled.

* |        |          |Note: Odd channels will read always 0 at complementary mode.

* |[7]     |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable

* |        |          |0 = Interrupt Flag accumulator interrupt Disabled.

* |        |          |1 = Interrupt Flag accumulator interrupt Enabled.

* |[13:8]  |PIENn     |PWM Period Point Interrupt Enable

* |        |          |Each bit n controls the corresponding PWM channel n.

* |        |          |0 = Period point interrupt Disabled.

* |        |          |1 = Period point interrupt Enabled.

* |        |          |Note1: When up-down counter type period point means center point.

* |        |          |Note2: Odd channels will read always 0 at complementary mode.

* |[15]    |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable

* |        |          |0 = Interrupt Flag accumulator interrupt Disabled.

* |        |          |1 = Interrupt Flag accumulator interrupt Enabled.

* |[21:16] |CMPUIENn  |PWM Compare Up Count Interrupt Enable

* |        |          |Each bit n controls the corresponding PWM channel n.

* |        |          |0 = Compare up count interrupt Disabled.

* |        |          |1 = Compare up count interrupt Enabled.

* |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.

* |[23]    |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable

* |        |          |0 = Interrupt Flag accumulator interrupt Disabled.

* |        |          |1 = Interrupt Flag accumulator interrupt Enabled.

* |[29:24] |CMPDIENn  |PWM Compare Down Count Interrupt Enable

* |        |          |Each bit n controls the corresponding PWM channel n.

* |        |          |0 = Compare down count interrupt Disabled.

* |        |          |1 = Compare down count interrupt Enabled.

* |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.

* @var PWM_T::INTEN1

* Offset: 0xE4  PWM Interrupt Enable Register 1

* ---------------------------------------------------------------------------------------------------

* |Bits    |Field     |Descriptions

* | :----: | :----:   | :---- |

* |[0]     |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)

* |        |          |0 = Edge-detect Brake interrupt for channel0/1 Disabled.

* |        |          |1 = Edge-detect Brake interrupt for channel0/1 Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[1]     |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)

* |        |          |0 = Edge-detect Brake interrupt for channel2/3 Disabled.

* |        |          |1 = Edge-detect Brake interrupt for channel2/3 Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[2]     |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)

* |        |          |0 = Edge-detect Brake interrupt for channel4/5 Disabled.

* |        |          |1 = Edge-detect Brake interrupt for channel4/5 Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[8]     |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)

* |        |          |0 = Level-detect Brake interrupt for channel0/1 Disabled.

* |        |          |1 = Level-detect Brake interrupt for channel0/1 Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[9]     |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)

* |        |          |0 = Level-detect Brake interrupt for channel2/3 Disabled.

* |        |          |1 = Level-detect Brake interrupt for channel2/3 Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* |[10]    |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)

* |        |          |0 = Level-detect Brake interrupt for channel4/5 Disabled.

* |        |          |1 = Level-detect Brake interrupt for channel4/5 Enabled.

* |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.

* @var PWM_T::INTSTS0

* Offset: 0xE8  PWM Interrupt Flag Register 0

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)

* | | |When falling capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::RCAPDAT1

* Offset: 0x214 PWM Rising Capture Data Register 1

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)

* | | |When rising capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::FCAPDAT1

* Offset: 0x218 PWM Falling Capture Data Register 1

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)

* | | |When falling capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::RCAPDAT2

* Offset: 0x21C PWM Rising Capture Data Register 2

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)

* | | |When rising capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::FCAPDAT2

* Offset: 0x220 PWM Falling Capture Data Register 2

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)

* | | |When falling capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::RCAPDAT3

* Offset: 0x224 PWM Rising Capture Data Register 3

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)

* | | |When rising capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::FCAPDAT3

* Offset: 0x228 PWM Falling Capture Data Register 3

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)

* | | |When falling capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::RCAPDAT4

* Offset: 0x22C PWM Rising Capture Data Register 4

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)

* | | |When rising capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::FCAPDAT4

* Offset: 0x230 PWM Falling Capture Data Register 4

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)

* | | |When falling capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::RCAPDAT5

* Offset: 0x234 PWM Rising Capture Data Register 5

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)

* | | |When rising capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::FCAPDAT5

* Offset: 0x238 PWM Falling Capture Data Register 5

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)

* | | |When falling capture condition happened, the PWM counter value will be saved in this register.

* @var PWM_T::PDMACTL

* Offset: 0x23C PWM PDMA Control Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[0] |CHEN0_1 |Channel 0/1 PDMA Enable

* | | |0 = Channel 0/1 PDMA function Disabled.

* | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.

* |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer

* | | |00 = Reserved.

* | | |01 = PWM_RCAPDAT0/1.

* | | |10 = PWM_FCAPDAT0/1.

* | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.

* |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order

* | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.

* | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory.

* | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory.

* |[4] |CHSEL0_1 |Select Channel 0/1 To Do PDMA Transfer

* | | |0 = Channel0.

* | | |1 = Channel1.

* |[8] |CHEN2_3 |Channel 2/3 PDMA Enable

* | | |0 = Channel 2/3 PDMA function Disabled.

* | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.

* |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer

* | | |00 = Reserved.

* | | |01 = PWM_RCAPDAT2/3.

* | | |10 = PWM_FCAPDAT2/3.

* | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.

* |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order

* | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.

* | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory.

* | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory.

* |[12] |CHSEL2_3 |Select Channel 2/3 To Do PDMA Transfer

* | | |0 = Channel2.

* | | |1 = Channel3.

* |[16] |CHEN4_5 |Channel 4/5 PDMA Enable

* | | |0 = Channel 4/5 PDMA function Disabled.

* | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.

* |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer

* | | |00 = Reserved.

* | | |01 = PWM_RCAPDAT4/5.

* | | |10 = PWM_FCAPDAT4/5.

* | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.

* |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order

* | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.

* | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory.

* | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory.

* |[20] |CHSEL4_5 |Select Channel 4/5 To Do PDMA Transfer

* | | |0 = Channel4.

* | | |1 = Channel5.

* @var PWM_T::PDMACAP0_1

* Offset: 0x240 PWM Capture Channel 01 PDMA Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |CAPBUF |PWM Capture PDMA Register

* | | |(Read Only)

* | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.

* @var PWM_T::PDMACAP2_3

* Offset: 0x244 PWM Capture Channel 23 PDMA Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |CAPBUF |PWM Capture PDMA Register

* | | |(Read Only)

* | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.

* @var PWM_T::PDMACAP4_5

* Offset: 0x248 PWM Capture Channel 45 PDMA Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |CAPBUF |PWM Capture PDMA Register

* | | |(Read Only)

* | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.

* @var PWM_T::CAPIEN

* Offset: 0x250 PWM Capture Interrupt Enable Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[5:0] |CAPRIENn |PWM Capture Rising Latch Interrupt Enable

* | | |Each bit n controls the corresponding PWM channel n.

* | | |0 = Capture rising edge latch interrupt Disabled.

* | | |1 = Capture rising edge latch interrupt Enabled.

* | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.

* |[13:8] |CAPFIENn |PWM Capture Falling Latch Interrupt Enable

* | | |Each bit n controls the corresponding PWM channel n.

* | | |0 = Capture falling edge latch interrupt Disabled.

* | | |1 = Capture falling edge latch interrupt Enabled.

* | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.

* @var PWM_T::CAPIF

* Offset: 0x254 PWM Capture Interrupt Flag Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[5:0] |CRLIFn |PWM Capture Rising Latch Interrupt Flag

* | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.

* | | |0 = No capture rising latch condition happened.

* | | |1 = Capture rising latch condition happened, this flag will be set to high.

* | | |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.

* |[13:8] |CFLIFn |PWM Capture Falling Latch Interrupt Flag

* | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.

* | | |0 = No capture falling latch condition happened.

* | | |1 = Capture falling latch condition happened, this flag will be set to high.

* | | |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.

* @var PWM_T::PBUF

* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |PBUF |PWM Period Register Buffer

* | | |(Read Only)

* | | |Used as PERIOD active register.

* @var PWM_T::CMPBUF

* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |CMPBUF |PWM Comparator Register Buffer

* | | |(Read Only)

* | | |Used as CMP active register.

* @var PWM_T::FTCBUF0_1

* Offset: 0x340 PWM FTCMPDAT0_1 Buffer

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)

* | | |Used as FTCMPDAT active register.

* @var PWM_T::FTCBUF2_3

* Offset: 0x344 PWM FTCMPDAT2_3 Buffer

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)

* | | |Used as FTCMPDAT active register.

* @var PWM_T::FTCBUF4_5

* Offset: 0x348 PWM FTCMPDAT4_5 Buffer

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)

* | | |Used as FTCMPDAT active register.

* @var PWM_T::FTCI

* Offset: 0x34C PWM FTCMPDAT Indicator Register

* ---------------------------------------------------------------------------------------------------

* |Bits |Field |Descriptions

* | :----: | :----: | :---- |

* |[2:0] |FTCMUn |PWM FTCMPDAT Up Indicator

* | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.

* | | |Each bit n controls the corresponding PWM channel n.

* |[10:8] |FTCMDn |PWM FTCMPDAT Down Indicator

* | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.

* | | |Each bit n controls the corresponding PWM channel n.

*/



__IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */

__IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */

__IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */

__IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */

__IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */

__IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */

__IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */

__IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */

__IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */

__IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */

__IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */

__I uint32_t RESERVE0[1]; 

__IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */

__I uint32_t RESERVE1[2]; 

__IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */

__I uint32_t RESERVE2[2]; 

__IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */

__IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */

__IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */

__I uint32_t RESERVE3[1]; 

__IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */

__IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */

__IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */

__I uint32_t RESERVE4[1]; 

__I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */

__I uint32_t RESERVE5[2]; 

__IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */

__IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */

__IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */

__IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */

__IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */

__IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */

__IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */

__IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */

__IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */

__IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */

__IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */

__O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */

__IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */

__IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */

__IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */

__IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */

__IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */

__IO uint32_t DACTRGEN; /* Offset: 0xF4 PWM Trigger DAC Enable Register */

__IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */

__IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */

__IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */

__IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */

__IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */

__I uint32_t RESERVE6[1]; 

__IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */

__O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */

__I uint32_t RESERVE7[2]; 

__IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */

__I uint32_t RESERVE8[55]; 

__IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */

__IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */

__I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */

__I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */

__I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */

__I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */

__I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */

__I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */

__I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */

__I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */

__I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */

__I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */

__I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */

__I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */

__I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */

__IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */

__I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */

__I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */

__I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */

__I uint32_t RESERVE9[1]; 

__IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */

__IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */

__I uint32_t RESERVE10[43];

__I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */

__I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */

__I uint32_t RESERVE11[3]; 

__I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */

__I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */

__I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */

__IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */



} PWM_T;

#define CLK_CLKSEL2_PWM0SEL_Pos          (0)                                               /*!< CLK_T::CLKSEL2: PWM0SEL Position          */

#define CLK_CLKSEL2_PWM0SEL_Msk          (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos)                /*!< CLK_T::CLKSEL2: PWM0SEL Mask              */



#define CLK_CLKSEL2_PWM1SEL_Pos          (1)                                               /*!< CLK_T::CLKSEL2: PWM1SEL Position          */

#define CLK_CLKSEL2_PWM1SEL_Msk          (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos)                /*!< CLK_T::CLKSEL2: PWM1SEL Mask     



#define CLK_CLKSEL2_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PLL */

#define CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PCLK0 */



CLK->APBCLK1 |= CLK_APBCLK1_PWM0CKEN_Msk;



/*---------------------------------------------------------------------------------------------------------*/

/* PWM clock frequency configuration */

/*---------------------------------------------------------------------------------------------------------*/

/* Select HCLK clock divider as 2 */

CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | CLK_CLKDIV0_HCLK(2);



/* PWM clock frequency can be set equal or double to HCLK by choosing case 1 or case 2 */

/* case 1.PWM clock frequency is set equal to HCLK: select PWM module clock source as PCLK */

CLK->CLKSEL2 = (CLK->CLKSEL2 & ~CLK_CLKSEL2_PWM0SEL_Msk) | CLK_CLKSEL2_PWM0SEL_PCLK0;

/* Set waveform generation */

    PWM0->WGCTL0 = 0x10000;

    PWM0->WGCTL1 = 0x20000;



    // Enable output of PWM0 channel 0

    PWM0->POEN |= PWM_POEN_POEN0_Msk;



    // Enable PWM0 channel 0 period interrupt, use channel 0 to measure time.

    PWM0->INTEN0 = (PWM0->INTEN0 & ~PWM_INTEN0_PIEN0_Msk) | PWM_INTEN0_PIEN0_Msk;

    NVIC_EnableIRQ(PWM0P0_IRQn);



    // Start

    PWM0->CNTEN |= PWM_CNTEN_CNTEN0_Msk;