[FPGA] altera FPGA内部VREFB Group引出脚是直接短路的吗

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 楼主 | 2018-12-1 16:12 | 显示全部楼层 |阅读模式
我用的cyclone10 484脚的FPGA,该FPGA每个bank有1个VREFB group,里面有四个引脚,由于没用的vref功能,想修改为IO口,datasheet里说用VREFB功能时,一个group里的4个引脚时直接短路的,必须一致,那接成IO口的话,是不是这4个引脚也必须是一个标号?麻烦各位了!
 楼主 | 2018-12-1 18:10 | 显示全部楼层
有了解的吗?官方手册上是这样写的
Each Intel Cyclone 10 LP I/O bank has a VREF bus to accommodate voltage-referenced I/O standards. Each VREF pin is the reference source for its VREF group.
• If you use a VREF group for voltage-referenced I/O standards, connect the VREF pin for that group to the appropriate voltage level.
• If you do not use all the VREF groups in the I/O bank for voltage-referenced I/Ostandards, you can use the VREF pin in the unused voltage-referenced groups as regular I/O pins.
• The VREF pins are shorted together within the same I/O bank. If you use multiple VREF groups in the same I/O bank, you must power all the VREF pins with the same voltage level.
For example, if you have SSTL-2 Class I input pins in I/O bank 1 and you place them all in the VREFB1N[0] group, you must power VREFB1N[0] with 1.25 V. You can use the remaining VREFB1N[1..3] pins, if available, as I/O pins.
Note: If you use VREF pins as regular I/Os, the VREF pins have higher pin capacitance than regular user I/O pins. This affects the timing if the pins are used as inputs and outputs.
 楼主 | 2018-12-1 18:12 | 显示全部楼层
看第三条应该是每个bank内部的VREFB引脚都是直接连在一起的(配置为IO口时应该也是只能代表一种信号,个人理解),但给的例子里,只用REFB0作为参考,而其他的三个可是设定为IO,这是不是有些矛盾?求指点
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