MAX32665行不行，有一路I2S，还有一个PDM接数字麦，有兴趣可以私信我，我是原厂。
High-Efficiency Microcontroller and Audio DSP for Wearable and Hearable Devices
Arm Cortex-M4 with FPU Up to 96MHz
Optional Second Arm Cortex-M4 with FPU
Optimized for Data Processing
Low-Power 7.3728MHz System Clock Option
1MB Flash, Organized into Dual Banks 2 x 512KB
560KB (448KB ECC) SRAM; 3 x 16KB Cache
Optional Error Correction Code (ECC-SEC-DED) for Cache, SRAM, and Internal Flash
Bluetooth 5 Low Energy Radio
Up to 2Mbps Data Throughput
Long Range (125kbps and 500kbps)
Rx Sensitivity: -95dbm; Tx Power: +9.5dbm
Single-Ended Antenna Connection
Power Management Maximizes Operating Time for Battery Applications
Integrated SIMO SMPS for Coin-Cell Operation
Dynamic Voltage Scaling Minimizes Active Core Power Consumption
27.3μA/MHz at 3.3V Executing from Cache
12.3μA at 3.3V Retention Current for 32KB SRAM
Selectable SRAM Retention in Low Power Modes with RTC Enabled
Multiple Peripherals for System Control
Three QSPI Master/Slave with Three Chip Selects Each, Three 4-Wire UARTs, Three I2C Master/Slave
QSPI (SPIXF) with Real-Time Flash Decryption
QSPI (SPIXR) RAM Interface Provides SRAM Expansion
8-Input, 10-Bit Delta-Sigma ADC 7.8ksps
USB 2.0 HS Engine with Internal Transceiver
PDM Interface Supports Two Digital Microphones
I2S with TDM, Six 32-Bit Timers, Two High-Speed Timers, 1-Wire Master, Sixteen Pulse Train (PWM) Engines
Secure Digital Interface Supports SD3.0/SDIO3.0/eMMC4.51
Secure Valuable IP/Data with Hardware Security
Trust Protection Unit (TPU) with MAA Supports Fast ECDSA and Modular Arithmetic
AES-128, -192, -256, DES, 3DES, Hardware
Accelerator
TRNG Seed Generator, SHA-2 Accelerator
Secure Bootloader
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以后要超低功耗考虑下华大
