基于寄存器操作的IO输出

/**************************************************************************//**

 * [url=home.php?mod=space&uid=288409]@file[/url]     main.c

 * [url=home.php?mod=space&uid=895143]@version[/url]  V3.00

 * $Revision: 7 $

 * $Date: 15/07/13 1:27p $

 * [url=home.php?mod=space&uid=247401]@brief[/url]    Show how to set GPIO pin mode and use pin data input/output control.

 *

 * @note

 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.

 ******************************************************************************/

#include <stdio.h>

#include "M051Series.h"





#define PLLCON_SETTING      CLK_PLLCON_50MHz_HXT

#define PLL_CLOCK           50000000





void SYS_Init(void)

{

    /*---------------------------------------------------------------------------------------------------------*/

    /* Init System Clock                                                                                       */

    /*---------------------------------------------------------------------------------------------------------*/



    /* Enable Internal RC 22.1184MHz clock */

    CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;



    /* Waiting for Internal RC clock ready */

    while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));



    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */

    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC;

    CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | CLK_CLKDIV_HCLK(1);



    /* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */

    CLK->PLLCON |= CLK_PLLCON_PD_Msk;    

    

    /* Enable external XTAL 12MHz clock */

    CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;



    /* Waiting for external XTAL clock ready */

    while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));



    /* Set core clock as PLL_CLOCK from PLL */

    CLK->PLLCON = PLLCON_SETTING;

    while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));

    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_PLL;



    /* Update System Core Clock */

    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */

    //SystemCoreClockUpdate();

    PllClock        = PLL_CLOCK;            // PLL

    SystemCoreClock = PLL_CLOCK / 1;        // HCLK

    CyclesPerUs     = PLL_CLOCK / 1000000;  // For CLK_SysTickDelay()



    /* Enable UART module clock */

    CLK->APBCLK |= CLK_APBCLK_UART0_EN_Msk;



    /* Select UART module clock source */

    CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_UART_S_Msk)) | CLK_CLKSEL1_UART_S_PLL;



    /*---------------------------------------------------------------------------------------------------------*/

    /* Init I/O Multi-function                                                                                 */

    /*---------------------------------------------------------------------------------------------------------*/



    /* Set P3 multi-function pins for UART0 RXD and TXD */

    SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);

    SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0);



}



void UART0_Init()

{

    /*---------------------------------------------------------------------------------------------------------*/

    /* Init UART                                                                                               */

    /*---------------------------------------------------------------------------------------------------------*/

    /* Reset UART0 */

    SYS->IPRSTC2 |=  SYS_IPRSTC2_UART0_RST_Msk;

    SYS->IPRSTC2 &= ~SYS_IPRSTC2_UART0_RST_Msk;



    /* Configure UART0 and set UART0 Baudrate */

    UART0->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(PLL_CLOCK, 115200);

    UART0->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;

}



/*---------------------------------------------------------------------------------------------------------*/

/* MAIN function                                                                                           */

/*---------------------------------------------------------------------------------------------------------*/

int main(void)

{

    int32_t i32Err;



    /* Unlock protected registers */

    SYS_UnlockReg();



    /* Init System, peripheral clock and multi-function I/O */

    SYS_Init();



    /* Lock protected registers */

    SYS_LockReg();



    /* Init UART0 for printf */

    UART0_Init();



    printf("\n\nCPU [url=home.php?mod=space&uid=72445]@[/url] %d Hz\n", SystemCoreClock);

    printf("+-------------------------------------------------+\n");

    printf("|    P1.2(Output) and P4.1(Input) Sample Code     |\n");

    printf("+-------------------------------------------------+\n\n");



    /* Configure P1.2 as Output mode and P4.1 as Input mode then close it */

    P1->PMD = (P1->PMD & (~GPIO_PMD_PMD2_Msk)) | (GPIO_PMD_OUTPUT << GPIO_PMD_PMD2_Pos);

    P4->PMD = (P4->PMD & (~GPIO_PMD_PMD1_Msk)) | (GPIO_PMD_INPUT << GPIO_PMD_PMD1_Pos);



    i32Err = 0;

    printf("GPIO P1.2(output mode) connect to P4.1(input mode) ......");



    /* Use Pin Data Input/Output Control to pull specified I/O or get I/O pin status */

    P12 = 0;

    if(P41 != 0)

    {

        i32Err = 1;

    }



    P12 = 1;

    if(P41 != 1)

    {

        i32Err = 1;

    }



    if(i32Err)

    {

        printf("  [FAIL].\n");

    }

    else

    {

        printf("  [OK].\n");

    }



    /* Configure P1.2 and P4.1 to default Quasi-bidirectional mode */

    P1->PMD = (P1->PMD & (~GPIO_PMD_PMD2_Msk)) | (GPIO_PMD_QUASI << GPIO_PMD_PMD2_Pos);

    P4->PMD = (P4->PMD & (~GPIO_PMD_PMD1_Msk)) | (GPIO_PMD_QUASI << GPIO_PMD_PMD1_Pos);



    while(1);

}



/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/