DAC芯片AD5547的使用求助！
最近我用FPGA控制AD5547设计一个DAC的电路，电路图是手册上给出的典型电路做的，但是死活没有任何输出，小弟实在不知是哪里除了问题，VHDL代码如下，希望谁能够帮帮忙。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DAC is port
(
clk : in std_logic;
a : out std_logic_vector(1 downto 0);
rs : inout std_logic;
wr : inout std_logic;
ldac: inout std_logic;
msb : out std_logic;
data: out std_logic_vector(15 downto 0)
);
end DAC;
architecture behavior of DAC is
signal dac_clk : std_logic:='0';
type StateType is (write_prepare,write,transfer,reset,end_reset);
signal present_state, next_state : StateType;
signal counter : std_logic_vector(11 downto 0):=(others=>'0');
signal temp : std_logic_vector(2 downto 0):="000";
begin
--initializing ad5547
a<= "00"; --a="00"代表只选择A通道，"01"选择AB通道，"11"只选择B通道，"10"都不选择
msb<= '0';
--rs<= '1';
--wr<= '1';
--ldac<= '0';
--分频
process(clk)
begin
if rising_edge(clk) then
if counter="000000000001" then
counter <= (others=>'0');
dac_clk <= not dac_clk;
else
counter <= counter+1;
end if;
end if;
end process;
--产生控制信号
process(dac_clk)
--variable temp : std_logic_vector(2 downto 0):="000";
begin
if rising_edge(dac_clk) then
if temp="000" then
temp <= temp+1;
wr<= '0';
elsif temp="001" then
temp <= temp+1;
wr<= '1';
elsif temp="010" then
temp <= temp+1;
ldac <= '1';
elsif temp="011" then
temp <= temp+1;
ldac <= '0';
rs<= '0';
elsif temp="100" then
temp <= "000";
rs<= '1';
else
temp <= temp +1;
end if;
end if;
end process;
data <= "1000111111111111";
end behavior; ...,LZ,你太有才了 本帖最后由 xym1020 于 2012-5-23 10:39 编辑
1# 强仔
这位大哥，你这个DA转换使用调试成功没？我最近也调试 调试不出来啊！求助！！！
我QQ297316265
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