仿真VCD文件系统任务的问题
我看夏 宇闻老师的书第97页有个例子，我打算做一下，可是不成功代码：
`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led;
// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led),
.rst_n(rst_n)
);
module M;
initial
$display("Displaying in %m");
endmodule
module top;
M m1();
M m2();
M m3();
endmodule
initial
$dumpfile("myfile.dmp");
initial
$dumpvars;
initial
$dumpvars(1,top); //?
initial
$dumpvars(2,top.m1);
initial
$dumpvars(0,top.m1);
initialbegin
$dumpon;
#100000 $dumpoff;
end
initial
$dumpall;
endmodule
提示出错：
其实就是两句话有问题
$dumpvars(1,top);
还有一句
$dumpall;
请个高手赐教，谢谢！
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