heweibig 发表于 2022-10-20 19:59

PIC18F4520奇怪的现象

18F4520做了一个简单的定时器控制的LED亮灭。在软件仿真的时候，定时时间，io引脚输出高低电平都是符合要求的。      问题：在硬件烧写后，程序老是不能正常跑，用手碰一下地线或者压一下LED，或者用手把板子拎起来，都能正常工作。我以为是我焊点虚焊的， 但是 在LED不亮灭的时候，我用示波器抓了一下LED输出脚的波形，波形没有输出。

heweibig 发表于 2022-10-20 20:03

VPP脚高电平，输入5V也是正常

huanghuac 发表于 2022-10-20 20:06

不是虚焊的问题

tian111 发表于 2022-10-20 20:09

配置位没有配置好

heweibig 发表于 2022-10-20 20:11

软件仿真的时候是正常的

heweibig 发表于 2022-10-20 20:13

VPP和VCC直接接了一个10k的电阻。LED输出用的是RA0和RA1.

pengf 发表于 2022-10-20 20:18

配置位贴上

renyaq 发表于 2022-10-20 20:20


// CONFIG1H
#pragma config OSC = INTIO7   // Oscillator Selection bits (Internal oscillator block, CLKO function on RA6, port function on RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = ON       // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)

// CONFIG2H
#pragma config WDT = OFF      // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = OFF       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF      // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF      // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF      // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF      // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF      // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF      // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

huangchui 发表于 2022-10-20 20:23

配置字看着还好。
1. RA0，RA1不接LED，用示波器量有没有问题？

huangchui 发表于 2022-10-20 20:26

2. 用一个极其简单的代码，就是翻转RA0，RA1，结果如何？

bqyj 发表于 2022-10-20 20:27

#pragma config LVP = OFF

Bowclad 发表于 2022-11-2 20:18

配置位没配置好吧

zwk34 发表于 2025-6-3 20:41

结果怎么样，如何解决问题的？

chenjun89 发表于 2025-6-3 20:50

从现象来看像是焊接的问题

kingTek 发表于 2025-6-10 07:56

很可能是主频不振所致，见我旧贴
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