verilog的问题
本帖最后由 fengyiyong 于 2012-11-26 11:41 编辑小弟初学verilog编了个8位乘法器，编译通过、但是仿真不对、乘数和被乘数却都是高阻、求大神帮助。附上三段代码
testbench：
`timescale 1ns/1ns
module testbench;
regaddend,adder;
initial
fork
addend=8'b00001111;
adder=8'b00010001;
join
add testbench(.addend_a(addend),.adder_a(adder));
adder test(.addend(addend),.adder(adder));
endmodule
add：
module add(a,b);
output a,b;
regd,addend_a,adder_a;
reg a,b;
always@(addend_a or adder_a)
fork
d=8'b11111111;
while(d)
begin
a=addend_a;
b=adder_a;
addend_a=(addend_a>>1);
adder_a=(adder_a>>1);
d=d<<1;
end
join
adder add(.a(a),.d(d),.b(b));
endmodule
adder：
module adder(adder,addend,sum);
inputaddend,adder;
outputsum;
regsum;
reg a,b,c,s;
regd;
initial
begin
sum=10'b0000000000;
c=1'b0;
end
always@(d)
begin
s=(~a)&(~b)&c+(~a)&b&(~c)+a&(~b)&(~c)+a&b&c;
c=a&b+a&(~b)&c+(~a)&b&c;
sum=s;
sum=c;
sum=sum>>1;
end
endmodule
页:
[1]