drsd 发表于 2009-5-11 23:20

求助高手--512位加法器

这是我写的512位加法器verilog程序，在quartus中运行错误是IO资源不够，这个要占用1500多个，但只能提供300多个，请教高手该怎么办啊，先谢谢了<br /><br />module&nbsp;adder(ina,inb,cin,outsum,cout);<br />output&nbsp;&nbsp;outsum;<br />output&nbsp;cout;<br />input&nbsp;&nbsp;ina,inb;<br />input&nbsp;cin;<br />wire&nbsp;c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15;<br /><br />full_add32&nbsp;fo(.ina(ina),.inb(inb),.cin(cin),.outsum(outsum),.cout(c1));<br />full_add32&nbsp;f1(.ina(ina),.inb(inb),.cin(c1),.outsum(outsum),.cout(c2));<br />full_add32&nbsp;f2(.ina(ina),.inb(inb),.cin(c2),.outsum(outsum),.cout(c3));<br />full_add32&nbsp;f3(.ina(ina),.inb(inb),.cin(c3),.outsum(outsum),.cout(c4));<br />full_add32&nbsp;f4(.ina(ina),.inb(inb),.cin(c4),.outsum(outsum),.cout(c5));<br />full_add32&nbsp;f5(.ina(ina),.inb(inb),.cin(c5),.outsum(outsum),.cout(c6));<br />full_add32&nbsp;f6(.ina(ina),.inb(inb),.cin(c6),.outsum(outsum),.cout(c7));<br />full_add32&nbsp;f7(.ina(ina),.inb(inb),.cin(c7),.outsum(outsum),.cout(c8));<br />full_add32&nbsp;f8(.ina(ina),.inb(inb),.cin(c8),.outsum(outsum),.cout(c9));<br />full_add32&nbsp;f9(.ina(ina),.inb(inb),.cin(c9),.outsum(outsum),.cout(c10));<br />full_add32&nbsp;f10(.ina(ina),.inb(inb),.cin(c10),.outsum(outsum),.cout(c11));<br />full_add32&nbsp;f11(.ina(ina),.inb(inb),.cin(c11),.outsum(outsum),.cout(c12));<br />full_add32&nbsp;f12(.ina(ina),.inb(inb),.cin(c12),.outsum(outsum),.cout(c13));<br />full_add32&nbsp;f13(.ina(ina),.inb(inb),.cin(c13),.outsum(outsum),.cout(c14));<br />full_add32&nbsp;f14(.ina(ina),.inb(inb),.cin(c14),.outsum(outsum),.cout(c15));<br />full_add32&nbsp;f15(.ina(ina),.inb(inb),.cin(c15),.outsum(outsum),.cout(cout));<br />endmodule<br /><br />module&nbsp;full_add32(ina,inb,cin,outsum,cout);<br />output&nbsp;outsum;<br />output&nbsp;cout;<br />input&nbsp;ina,inb;<br />input&nbsp;cin;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;assign&nbsp;{cout,outsum}=ina+inb+cin;<br />endmodule

patrick007 发表于 2009-5-12 00:25

re

512*(2in+1out)&nbsp;&nbsp;.......<br /><br />try&nbsp;64bits&nbsp;in&nbsp;and&nbsp;out,&nbsp;and&nbsp;use&nbsp;comb&nbsp;logic&nbsp;to&nbsp;<br /><br /><br />7+7&nbsp;=&nbsp;(3+3+1)+(3+3+1)<br />

Fourier00 发表于 2009-5-15 20:11

lz是为了让这个玩意编译过去

lz是为了让这个玩意编译过去？&nbsp;<br />可以试试大一点的片子，或者用虚拟pin

beinghu 发表于 2009-7-3 15:56

用个top模块包起来

top模块的io少于300就没事了

氧化 发表于 2009-7-3 21:15

Fourier00 正解！

Fourier00&nbsp;正解！
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