寻乐的狼 发表于 2009-6-23 16:04

下面这个代码中generic什么意思

请问下面这个代码中generic是什么用<br />library&nbsp;IEEE;<br />use&nbsp;IEEE.std_logic_1164.all;<br />use&nbsp;IEEE.std_logic_arith.all;<br />use&nbsp;IEEE.std_logic_unsigned.all;<br />use&nbsp;work.LPM_COMPONENTS.all;<br /><br />entity&nbsp;LPM_CONSTANT&nbsp;is<br />&nbsp;&nbsp;&nbsp;&nbsp;generic&nbsp;(LPM_WIDTH&nbsp;:&nbsp;natural;&nbsp;&nbsp;&nbsp;&nbsp;--&nbsp;MUST&nbsp;be&nbsp;greater&nbsp;than&nbsp;0<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LPM_CVALUE&nbsp;:&nbsp;natural;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LPM_STRENGTH&nbsp;:&nbsp;string&nbsp;:=&nbsp;&quot;UNUSED&quot;;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LPM_TYPE&nbsp;:&nbsp;string&nbsp;:=&nbsp;&quot;LPM_CONSTANT&quot;;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;LPM_HINT&nbsp;:&nbsp;string&nbsp;:=&nbsp;&quot;UNUSED&quot;);<br />&nbsp;&nbsp;&nbsp;&nbsp;port&nbsp;(RESULT&nbsp;:&nbsp;out&nbsp;std_logic_vector(LPM_WIDTH-1&nbsp;downto&nbsp;0));<br />end&nbsp;LPM_CONSTANT;<br /><br />architecture&nbsp;LPM_SYN&nbsp;of&nbsp;LPM_CONSTANT&nbsp;is<br />begin<br /><br />&nbsp;&nbsp;&nbsp;&nbsp;RESULT&nbsp;&lt=&nbsp;conv_std_logic_vector(LPM_CVALUE,&nbsp;LPM_WIDTH);<br /><br />end&nbsp;LPM_SYN;<br />

beinghu 发表于 2009-7-3 15:49

等效于verilog中的parameter

参数化设计用的&nbsp;。多用&nbsp;google搜索

f4335089 发表于 2009-7-5 20:04

类属性说明语句的关键字

端口界面常数，常以一种说明的形式放在实体或块结构体前的说明部分。类属的值可由设计实体外部提供，设计者可以在调用时在说明类属的值。便于调用和修改。

jinfengmusic 发表于 2009-7-19 20:48

同意！

更加同意3楼的说法！

shuai12 发表于 2009-8-5 21:45

参数传递映射用的
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