问答

大家好，第一次接触这个单片机，按手册上说的，调试引脚都是独立的，没有连接任何电阻电容，但是还是无法仿真。手册说OCDEN=0；需要代码里配置为0，还是用Keil调试时，调试器自动就把OCDEN配置为0了？

使用IAR下载调试时，界面卡死，无法下载，用JLINK SWD JTAG模式都试了，还是无法下载？

（1）程序下载没有问题；（2）设置断点仿真，断点停了之后，程序复位重新运行，无法仿真。

Load "C:\\Users\\hppen\\Desktop\\HT32Fxx\\example\\GPIO\\InputOutput\\MDK_ARMv5\\Obj\\HT32.axf" Cannot access Memory ([url=home.php?mod=space&uid=72445]@[/url] 0x00000000, Write, Acc Size: 4 Byte) Cannot access Memory (@ 0x00001000, Write, Acc Size: 4 Byte) *** error 57: illegal address (0x00001000) Include "C:\\Users\\hppen\\Desktop\\HT32Fxx\\example\\GPIO\\InputOutput\\MDK_ARMv5\\HT32F5xxxx_01_DebugSupport.ini" /*----------------------------------------------------------------------------------------------------------*/ /* Holtek Semiconductor Inc. */ /* */ /* Copyright (C) Holtek Semiconductor Inc. */ /* All rights reserved. */ /* */ /*------------------------------------------------------------------------------------------------------------ File Name : HT32F5xxxx_01_DebugSupport.ini Version : V1.03 Date : 2019-07-08 Description : Debug Support Initialization file. ------------------------------------------------------------------------------------------------------------*/ // Supported Device // ======================================== // HT32F5xxxx // <<< Use Configuration Wizard in Context Menu >>> FUNC void DebugSupport (void) { // Configure MCU Debug Control Register // Debug Sleep Mode (DBSLP) // LDO = On, FCLK = On, and HCLK = On in Sleep mode // Debug Deep-Sleep Mode 1 (DBDSLP1) // LDO = On, FCLK = On, and HCLK = On in Deep-Sleep mode 1 // Debug Deep-Sleep Mode 2 (DBDSLP2) // LDO = On, FCLK = On, and HCLK = On in Deep-Sleep mode 2 // Debug Power-Down Mode (DBPD) // LDO = On, FCLK = On, and HCLK = On in Power-Down mode // WDT Debug Mode Enable (DBWDT) // WDT Timer counter is stopped when the core is halted // MCTM0 Debug Mode Enable (DBMCTM0) // MCTM0 Timer counter is stopped when the core is halted // GPTM0 Debug Mode Enable (DBGPTM0) // GPTM0 Timer counter is stopped when the core is halted // GPTM1 Debug Mode Enable (DBGPTM1) // GPTM1 Timer counter is stopped when the core is halted // USART0 Debug Mode Enable (DBUSART0) // USART0 Rx FIFO timeout counter is stopped when the core is halted // USART1 Debug Mode Enable (DBUSART1) // USART1 Rx FIFO timeout counter is stopped when the core is halted // UART0 Debug Mode Enable (DBUART0) // UART0 Rx FIFO timeout counter is stopped when the core is halted // UART1 Debug Mode Enable (DBUART1) // UART1 Rx FIFO timeout counter is stopped when the core is halted // UART2 Debug Mode Enable (DBUART2) // UART2 Rx FIFO timeout counter is stopped when the core is halted // UART3 Debug Mode Enable (DBUART3) // UART3 Rx FIFO timeout counter is stopped when the core is halted // SPI0 Debug Mode Enable (DBSPI0) // SPI0 Rx FIFO timeout counter is stopped when the core is halted // SPI1 Debug Mode Enable (DBSPI1) // SPI1 Rx FIFO timeout counter is stopped when the core is halted // I2C0 Debug Mode Enable (DBI2C0) // I2C0 timeout counter is stopped when the core is halted // I2C1 Debug Mode Enable (DBI2C1) // I2C1 timeout counter is stopped when the core is halted // I2C2 Debug Mode Enable (DBI2C2) // I2C2 timeout counter is stopped when the core is halted // SCI0 Debug Mode Enable (DBSCI0) // SCI0 Waiting Time counter is stopped when the core is halted // SCI1 Debug Mode Enable (DBSCI1) // SCI1 Waiting Time counter is stopped when the core is halted // BFTM0 Debug Mode Enable (DBBFTM0) // BFTM0 Timer counter is stopped when the core is halted // BFTM1 Debug Mode Enable (DBBFTM1) // BFTM1 Timer counter is stopped when the core is halted // SCTM0 Debug Mode Enable (DBSCTM0) // SCTM0 Timer counter is stopped when the core is halted // SCTM1 Debug Mode Enable (DBSCTM1) // SCTM1 Timer counter is stopped when the core is halted // SCTM2 Debug Mode Enable (DBSCTM2) // SCTM2 Timer counter is stopped when the core is halted // SCTM3 Debug Mode Enable (DBSCTM3) // SCTM3 Timer counter is stopped when the core is halted // PWM0 Debug Mode Enable (DBPWM0) // PWM0 counter is stopped when the core is halted // PWM1 Debug Mode Enable (DBPWM1) // PWM1 counter is stopped when the core is halted // if (0) { _WDWORD(0x40088304, 0x00000000); } } DebugSupport(); /*----------------------------------------------------------------------------------------------------------*/ /* Uncomment to debug stack/heap underflow, overflow, and overwrite */ /*----------------------------------------------------------------------------------------------------------*/ //BS Write __HT_check_sp, 2 //BS Write __HT_check_heap, 2 /*----------------------------------------------------------------------------------------------------------*/ /* Load debug symbol */ /*----------------------------------------------------------------------------------------------------------*/ //LOAD %L INCREMENTAL