问答

哪位大佬知道Multisim怎么搭建NE565的锁相环芯片呀？找了官网的芯片内部电路图，但是有的电阻没有标明阻值该怎么办？求大佬指点！跪谢了！

[i=s] 本帖最后由 awbl 于 2023-8-27 13:33 编辑 [/i] 在学习FIR的过程中遇到了仿真问题，大家帮忙看一下。1、modelsim版本：modelsim-Altera 10.3d 2、quartus版本 ：Quartus II 15.0 (64-bit) 3、主程序fir.v:[list=1] [*] module fir( [*] clk , [*] rst_n , [*] key , [*] dac_mode , [*] dac_sleep , [*] dac_clka , [*] dac_dat_a , [*] dac_wra , [*] dac_clkb , [*] dac_dat_b , [*] dac_wrb [*]); [*] [*]input clk ; [*]input rst_n ; [*]input [7:0] key ; [*]output dac_mode ; [*]output dac_sleep ; [*]output dac_clka ; [*]output [7:0] dac_dat_a ; [*]output dac_wra ; [*]output dac_clkb ; [*]output [7:0] dac_dat_b ; [*]output dac_wrb ; [*] [*]//信号类型定义。 [*]reg [7:0] sin_data ; [*]reg [31:0] cnt1 ; [*]wire add_cnt1 ; [*]wire end_cnt1 ; [*]wire [16:0] addr_temp ; [*]wire [6:0] addr ; [*]reg [12:0] x ; [*]reg [7:0] dac_dat_a ; [*]wire dac_sleep ; [*]wire dac_mode ; [*]wire dac_clka ; [*]reg [1:0] cnt0 ; [*]wire add_cnt0 ; [*]wire end_cnt0 ; [*]wire [7:0] fir_dout ; [*]wire fir_dout_vld; [*]reg [7:0] dac_dat_b ; [*]wire dac_clkb ; [*]wire dac_wrb ; [*]wire [7:0] fir_din ; [*]wire [7:0] fir_dout2 ; [*]//设计正弦信号。 [*]always @(*) begin [*] case(addr) [*]0: sin_data = 8'h7F; [*]1: sin_data = 8'h85; [*]2: sin_data = 8'h8C; [*]3: sin_data = 8'h92; [*]4: sin_data = 8'h98; [*]5: sin_data = 8'h9E; [*]6: sin_data = 8'hA4; [*]7: sin_data = 8'hAA; [*]8: sin_data = 8'hB0; [*]9: sin_data = 8'hB6; [*]10: sin_data = 8'hBC; [*]11: sin_data = 8'hC1; [*]12: sin_data = 8'hC6; [*]13: sin_data = 8'hCB; [*]14: sin_data = 8'hD0; [*]15: sin_data = 8'hD5; [*]16: sin_data = 8'hDA; [*]17: sin_data = 8'hDE; [*]18: sin_data = 8'hE2; [*]19: sin_data = 8'hE6; [*]20: sin_data = 8'hEA; [*]21: sin_data = 8'hED; [*]22: sin_data = 8'hF0; [*]23: sin_data = 8'hF3; [*]24: sin_data = 8'hF5; [*]25: sin_data = 8'hF7; [*]26: sin_data = 8'hF9; [*]27: sin_data = 8'hFB; [*]28: sin_data = 8'hFC; [*]29: sin_data = 8'hFD; [*]30: sin_data = 8'hFE; [*]31: sin_data = 8'hFE; [*]32: sin_data = 8'hFE; [*]33: sin_data = 8'hFE; [*]34: sin_data = 8'hFE; [*]35: sin_data = 8'hFD; [*]36: sin_data = 8'hFC; [*]37: sin_data = 8'hFA; [*]38: sin_data = 8'hF8; [*]39: sin_data = 8'hF6; [*]40: sin_data = 8'hF4; [*]41: sin_data = 8'hF1; [*]42: sin_data = 8'hEF; [*]43: sin_data = 8'hEB; [*]44: sin_data = 8'hE8; [*]45: sin_data = 8'hE4; [*]46: sin_data = 8'hE0; [*]47: sin_data = 8'hDC; [*]48: sin_data = 8'hD8; [*]49: sin_data = 8'hD3; [*]50: sin_data = 8'hCE; [*]51: sin_data = 8'hC9; [*]52: sin_data = 8'hC4; [*]53: sin_data = 8'hBE; [*]54: sin_data = 8'hB9; [*]55: sin_data = 8'hB3; [*]56: sin_data = 8'hAD; [*]57: sin_data = 8'hA7; [*]58: sin_data = 8'hA1; [*]59: sin_data = 8'h9B; [*]60: sin_data = 8'h95; [*]61: sin_data = 8'h8F; [*]62: sin_data = 8'h89; [*]63: sin_data = 8'h82; [*]64: sin_data = 8'h7D; [*]65: sin_data = 8'h77; [*]66: sin_data = 8'h70; [*]67: sin_data = 8'h6A; [*]68: sin_data = 8'h64; [*]69: sin_data = 8'h5E; [*]70: sin_data = 8'h58; [*]71: sin_data = 8'h52; [*]72: sin_data = 8'h4C; [*]73: sin_data = 8'h46; [*]74: sin_data = 8'h41; [*]75: sin_data = 8'h3C; [*]76: sin_data = 8'h36; [*]77: sin_data = 8'h31; [*]78: sin_data = 8'h2C; [*]79: sin_data = 8'h28; [*]80: sin_data = 8'h23; [*]81: sin_data = 8'h1F; [*]82: sin_data = 8'h1B; [*]83: sin_data = 8'h17; [*]84: sin_data = 8'h14; [*]85: sin_data = 8'h11; [*]86: sin_data = 8'hE ; [*]87: sin_data = 8'hB ; [*]88: sin_data = 8'h9 ; [*]89: sin_data = 8'h7 ; [*]90: sin_data = 8'h5 ; [*]91: sin_data = 8'h3 ; [*]92: sin_data = 8'h2 ; [*]93: sin_data = 8'h1 ; [*]94: sin_data = 8'h1 ; [*]95: sin_data = 8'h1 ; [*]96: sin_data = 8'h1 ; [*]97: sin_data = 8'h1 ; [*]98: sin_data = 8'h2 ; [*]99: sin_data = 8'h3 ; [*]100: sin_data = 8'h4 ; [*]101: sin_data = 8'h6 ; [*]102: sin_data = 8'h7 ; [*]103: sin_data = 8'hA ; [*]104: sin_data = 8'hC ; [*]105: sin_data = 8'hF ; [*]106: sin_data = 8'h12; [*]107: sin_data = 8'h15; [*]108: sin_data = 8'h19; [*]109: sin_data = 8'h1D; [*]110: sin_data = 8'h21; [*]111: sin_data = 8'h25; [*]112: sin_data = 8'h2A; [*]113: sin_data = 8'h2E; [*]114: sin_data = 8'h33; [*]115: sin_data = 8'h38; [*]116: sin_data = 8'h3E; [*]117: sin_data = 8'h43; [*]118: sin_data = 8'h49; [*]119: sin_data = 8'h4E; [*]120: sin_data = 8'h54; [*]121: sin_data = 8'h5A; [*]122: sin_data = 8'h60; [*]123: sin_data = 8'h67; [*]124: sin_data = 8'h6D; [*]125: sin_data = 8'h73; [*]126: sin_data = 8'h79; [*]127: sin_data = 8'h7F; [*] endcase [*]end [*] [*]always @(posedge clk or negedge rst_n)begin [*] if(!rst_n)begin [*] cnt1 <= 0; [*] end [*] else if(add_cnt1)begin [*] if(end_cnt1) [*] cnt1 <= 0; [*] else [*] cnt1 <= cnt1 + 1; [*] end [*]end [*] [*]assign add_cnt1 = 1 ; [*]assign end_cnt1 = 0 ; [*] [*] [*]always @(*) begin [*] if(key == 0)begin [*] x = 262 ; [*] end [*] else if(key == 1)begin [*] x = 524 ; [*] end [*] else if(key == 2)begin [*] x = 786 ; [*] end [*] else if(key == 3)begin [*] x = 1029 ; [*] end [*] else if(key == 4)begin [*] x = 1311 ; [*] end [*] else if(key == 5)begin [*] x = 1573 ; [*] end [*] else if(key == 6)begin [*] x = 1835 ; [*] end [*] else begin [*] x = 2097 ; [*] end [*]end [*]assign addr_temp = cnt1 * x ; [*]assign addr = addr_temp >> 10 ; [*] [*] [*]//A通道输出。 [*]always @(posedge clk or negedge rst_n)begin [*] if(rst_n==1'b0)begin [*] dac_dat_a <= 0 ; [*] end [*] else begin [*] dac_dat_a <= 255 - sin_data ; [*] end [*]end [*] [*]assign dac_sleep = 0 ; [*]assign dac_mode = 1 ; [*]assign dac_wra = dac_clka ; [*]assign dac_clka = ~clk ; [*] [*]//设计滤波器。 [*]always @(posedge clk or negedge rst_n)begin [*] if(!rst_n)begin [*] cnt0 <= 0; [*] end [*] else if(add_cnt0)begin [*] if(end_cnt0) [*] cnt0 <= 0; [*] else [*] cnt0 <= cnt0 + 1; [*] end [*]end [*] [*]assign add_cnt0 = 1 ; [*]assign end_cnt0 = add_cnt0 && cnt0== 4 - 1 ; [*]assign fir_din = sin_data - 128 ; [*]ip_fir_1 module_2( [*] .clk (clk ), [*] .reset_n (rst_n ), [*] .ast_sink_data (fir_din ), [*] .ast_sink_valid (end_cnt0 ), [*] .ast_sink_error (2'b00 ), [*] .ast_source_data (fir_dout ), [*] .ast_source_valid (fir_dout_vld ), [*] .ast_source_error ( ) [*] ); [*]assign fir_dout2 = fir_dout + 128 ; [*]always @(posedge clk or negedge rst_n)begin [*] if(rst_n==1'b0)begin [*] dac_dat_b <= 0 ; [*] end [*] else if(fir_dout_vld) begin [*] dac_dat_b <= 255 - fir_dout2 ; [*] end [*]end [*] [*]assign dac_wrb = dac_clkb ; [*]assign dac_clkb = ~clk ; [*]endmodule [/list] 4、IP核文件 ip_fir_1.v : [list=1] [*]`timescale 1 ps / 1 ps [*]module ip_fir_1 ( [*] input wire clk, // clk.clk [*] input wire reset_n, // rst.reset_n [*] input wire [7:0] ast_sink_data, // avalon_streaming_sink.data [*] input wire ast_sink_valid, // .valid [*] input wire [1:0] ast_sink_error, // .error [*] output wire [7:0] ast_source_data, // avalon_streaming_source.data [*] output wire ast_source_valid, // .valid [*] output wire [1:0] ast_source_error // .error [*] ); [*] [*] ip_fir_1_0002 ip_fir_1_inst ( [*] .clk (clk), // clk.clk [*] .reset_n (reset_n), // rst.reset_n [*] .ast_sink_data (ast_sink_data), // avalon_streaming_sink.data [*] .ast_sink_valid (ast_sink_valid), // .valid [*] .ast_sink_error (ast_sink_error), // .error [*] .ast_source_data (ast_source_data), // avalon_streaming_source.data [*] .ast_source_valid (ast_source_valid), // .valid [*] .ast_source_error (ast_source_error) // .error [*] ); [*] [*]endmodule [/list] 5、测试文件 test_fir.v : [list=1] [*]`timescale 1 ns/1 ns [*] [*]module test_fir(); [*] [*]//时钟和复位 [*]reg clk ; [*]reg rst_n; [*] [*]//uut的输入信号 [*]reg[7:0] key ; [*] [*]//uut的输出信号 [*]wire dac_mode ; [*]wire dac_sleep ; [*]wire dac_clka ; [*]wire [7:0] dac_dat_a ; [*]wire dac_wra ; [*]wire dac_clkb ; [*]wire [7:0] dac_dat_b ; [*]wire dac_wrb ; [*] [*] [*]//时钟周期，单位为ns，可在此修改时钟周期。 [*]parameter CYCLE = 200; [*] [*]//复位时间，此时表示复位3个时钟周期的时间。 [*]parameter RST_TIME = 3 ; [*] [*]//待测试的模块例化 [*]fir uut( [*] .clk (clk ), [*] .rst_n (rst_n ), [*] .key (key ), [*] .dac_mode (dac_mode ), [*] .dac_sleep (dac_sleep ), [*] .dac_clka (dac_clka ), [*] .dac_dat_a (dac_dat_a ), [*] .dac_wra (dac_wra ), [*] .dac_clkb (dac_clkb ), [*] .dac_dat_b (dac_dat_b ), [*] .dac_wrb (dac_wrb ) [*] [*]); [*] [*] [*]//生成本地时钟50M [*]initial begin [*] clk = 0; [*] forever [*] #(CYCLE/2) [*] clk=~clk; [*]end [*] [*]//产生复位信号 [*]initial begin [*] rst_n = 1; [*] #2; [*] rst_n = 0; [*] #(CYCLE*RST_TIME); [*] rst_n = 1; [*]end [*] [*]//输入信号key赋值方式 [*]initial begin [*] forever begin [*] #(10000*CYCLE); [*] //赋初值 [*] key = 0; [*] #(10000*CYCLE); [*] key = 1; [*] #(10000*CYCLE); [*] key = 2; [*] #(10000*CYCLE); [*] key = 3; [*] #(10000*CYCLE); [*] key = 4; [*] #(10000*CYCLE); [*] key = 5; [*] #(10000*CYCLE); [*] key = 6; [*] #(10000*CYCLE); [*] key = 7; [*]end [*]end [*]endmodule [/list] 6、quartus和modelsim联合仿真报错如下图： [attach]2152750[/attach] [attach]2152748[/attach] 恳请各位指正！！

[i=s] 本帖最后由 awbl 于 2023-8-26 17:40 编辑 [/i] [color=#444444][backcolor=rgb(255, 255, 255)][font=Tahoma, "]在跟着B站视频学习到FIR时，仿真遇到问题。[/font][/backcolor][/color] [color=#444444][backcolor=rgb(255, 255, 255)][font=Tahoma, "]1、quartus版本：Quartus (Quartus Prime 18.1) Lite Edition[/font][/backcolor][/color] [color=#444444][backcolor=rgb(255, 255, 255)][font=Tahoma, "]2、modelsim是从altera官网下载的pro 18.1 ,已经解锁。[/font][/backcolor][/color] [color=#444444][backcolor=rgb(255, 255, 255)][font=Tahoma, "]3、联合仿真时出现以下错误： [/font][/backcolor][/color][img=600,0]http://www.fpgabbs.cn/data/attachment/forum/202308/25/171117k153sus5p2i5js3l.png[/img] [align=left][font=Arial][float=right] [/float][/font][/align][color=#444444][backcolor=rgb(255, 255, 255)][/backcolor][/color][img=598,0]http://www.fpgabbs.cn/data/attachment/forum/202308/25/171117z64f68j1o6tf0jz6.png[/img][color=#444444][backcolor=rgb(255, 255, 255)][/backcolor][/color] [color=#444444][backcolor=rgb(255, 255, 255)][font=Tahoma, "]4、单独仿真时出现以下错误： [/font][/backcolor][/color][img=600,0]http://www.fpgabbs.cn/data/attachment/forum/202308/25/171142uglnnhinm9ph5mnm.png[/img] [color=#444444][backcolor=rgb(255, 255, 255)][font=Tahoma, "]诸位大佬指点迷经，感激不尽[/font][/backcolor][/color]{:cry:}

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S7EmI6/DhCOjc+D7UGhtJW04YHRAGPvKICxZzTA4PmhUM4dzyfPrwrF3LM/UCh9hXyHfKhGd/xix/xP584vuM3n474kd7F4csQ/tgs4MBfYPzuPA1mA0TwL8MPBDwGFGcBBB4ffBxg/vgswWt4BGEffBhgn3gEYJ98DGO0zAQYaABdMuMUAGI0AGPSvTgZ93oGxDgCDPgDF2AiAsRkA4xsAjC0ACJymkOtRyO0pZLkUcn8UrhFg/ShkvSnk8VD4mQMxdrYHhWwnCtl+FLJdKWR7U8jzQCHPD4U8byp05lPO9YFZgAvhEx5fmQuQD9Uw8eWxPs5jPi0IiRD/2Oyzgf3vA8f3AdgbACorB/sBxIEDACpFM4BTEZWOm9vHMQ8BPkC+s/99kC/Vwos4in1kt9jOXW5ZIsSnlyEey3ZTqzWt2AbGBuX4APlQrbxss8sQvyu9CdWMpXNfl847flcN6S27hvjmffSxvY++qyxYRHgiR1dGVRM/7HmCJqgrvvu8qxDoVB0HE1+SI5fLqXfT0Tvq+H11XSGsynfuVQvx161bB4PasUEY8fnttF0lrLqXbVYL8U/VncvoXd5dQTHiy3fRd6V4GNcqLTe/nWfuFKr+ToGJP2TIEAwbNgyjRo3CG2+84f6bj8oNotkgsd/OM7tbebubsVuh3Zj4f3tjMmbMnI3PlzRiQ25rh//eXCm/SXeq1In0f/yw4wVNkLncK3RcQ+bKbMLEl5d7HfEcHObvp3K5Iv74VUAcMMSvzMHNAuFvPyb+HSOm4J6XG/DIW014pmFbLD4r/f5UJnJU3V3iN+4CKoUhvr/jGkJXZhcm/tNjp2DMWw2Y8nETZjVtq9hfpb/TAlBLf4b45nLvlLncM8SPb2kyxDfEN8TfZT/qxker6pdkiG+Ib4h/ihF/nmWh6dGn3dVl/aqt2LB+l5umyLql6zH/Jz8B1Z132mkqXDuL3vlg/xniG+KfMsT/Td1YXPPnN3HNXR/h6vuW4jePbMcVD3yHy+6r/Hm/2DP+c2/vgcTwqXvwl4m78cCru/DfY77Hn0buRP8RO9D7ye0enZhkcYdE5vn/cDrWfvIllt/9gCL1wjPOBC0A/Pdl75tU/pJrrsfye4fa8Suv5mL7+/g0aHnRwXE5WIqHDdhc7lV2iVVrl4D0lt1SxsyXe7+7ZyJuGToLdcO+wIDnNmLQ+BYMfOkwLhm43Nd/2Y9LCcOIP2kBMGFeO175tA1jPzqJzKxWPPf+CTw97Tgee/MYHpx0BPe+3uLRyWVZzBEmu9rNaUd3sPR3t6ieVk+YpvIW/OM/qZ1//drt9u5/2mkqTZWK7vhE9igDrhriT6sTv5hrodeIppIcrBQnzNeZhjrxCzuW1QsjmqIQn9rXYVroiYPqRZVdqh5Jyg7XgV+Dnrepfxsm/i9vHoNet0zBL/44Gz0Gfql2etrtL/rTksSJz5vg01N24+EJu3H3OHun7zd8B3772He40jl5kD6sU8x894hrHPBfityfd+8BJjod7WnXX3jOuapsxfCM22bZbXeovGV1f1Z5ocSPMuCqIL4ifSmE8neyMCfMl2ukSaxfrZ/QhSLKuJKUHa4HEz9s52fiT5w0BTNmzsHCz5dh9ddbsGv/CSxdvQWX/tsdiRL/zWxjwacE2wGcPNmO4yfa0XK0DQd/bMUPB1s9Orms64AILQC08y/62c/dBWHjFnpTkv1Hz/dUvvCss1VGUeJHHXDnE78JI3oV2x3J0fnHKmQ9mwB1db1g9RqBJkUuUbdums+JQScNpXnB8Wtr18/3Ids78RH5k0rdNCZOYZn3BEPlzphcPe02+b7ILjxueQJyZDsnlaYRvZyTEo+DdUgmlMQvRn4m/oSJf0ffvn0xd9EypNNpbN9zvEOIP3nGEkX8+++/H4yTbe1unPN27z/h0YlJ1xHhylGvKmITudXz/5zPC7pd/dqbWD15ejjxecD8+eP29nbQgI+3tqHlWBuOHm/DD4dawQPudOI3jUAvl7iFzjqtTjg97dBuXZs8klBU1yZf0GLiQxpHnn9bvQ/Z3i6zmLie00OxsmaU1pe0BcljYus6cL6sn1xcJ34Q+Zn4r0+YjJmz5mDBoka14+8+0DE7/t+mL/Ts+G1twInWduX/h1pOqrD58EnsO9gKqVMB8xLMoN2djvFf/Ooql9zU3ZCHhynoXRfd8XnANCEzZszAiZPtOOoQ3m/A1U186eTkzDIt41yW3yFp/PkdmIlAbWQdJo2ez239+uBTRyVlUoegvprRrBYTruvXr3Mq4MUn1kcKtpk31Imff4zy1pPEpx2fiE87viRZsQs8vR9K6/WLXe698tZn7o7f1g7PTn/4yEk3LYn/5Jlnoufpp+t8c9N+OrmFMUWI9LIfKbYo8XnA7e3A9ddfj8bGRrW60WAJtOPLla7Tie8hs9d5vESnMkk2GdfLdDmc1ttEzZftZVzvP0pZgA4Fpxs/4ttt7eM+L2IsL5lQOmUQ6Smfif/GxL8X7PgLm0p7xpd96aSndDHij53SoIhPPGilze+4fdqVoeTBI926YeJ11xUlPpFQ6iRJGSXe59U1mLx4Z2CTsnZ8HnBrWzuOnWhTijL5edBywJ1P/GYox3WP8OSw0zDCudUvftRnMlAbe/eTR/9Cx9QJyeQIaqvXl2mK5x9DvGOQ9ezx5G/5S+yLiM87udr5eay6bB47l/OYkgnZ8Qtt6+2Pif/a65PVM77c8UslPpGb+vMjfRjxX5w0G0R6fpbnkHxfgnb8u884A6MuuyyU9MxU0qmSv7MfXwzrf+bhly8s910AyiI+D5huLnnHp8HJwVYb8cmJ8pdUdLSVu5dNMNvhpHP7EIDuC9yjvJTBTunTho/Hvm31+jJtx9VlnOqzmG6yXTOaS+7LOebX1Yl/D0pZFOc6fpeZPO74QpqHMNJTORN//GuT8c57szF3oX2rT0f9KMQPIn0pxOcb/B+P2Tf4xANGz5490atXL/xLjx741fnn4+pUCumBAyvhc9G2RPQg6AtA2cSnAdME0TP+D4dOqOcqHrAMaRKqYccvxZGqr44kYHzEqr5xljc2Jv64VyepHf+T+UvdZ/yOIj5daB851ga622IekM9fddVVGDx4MIYOHYp+/fq56N27N2644YaiBC63MIj0lH/uE1/gmTlbse7bQ0p82cSnQUrQYINgiF+eY3vvG8qV0XXbMfEf/2sGI8dOwutTZ+Ld2YvVbt9RxKfPC0hQv+eddx5uvPFGl+xEfCI85d16663o06dPudwuuR0f9XXCs4BPP1/j3iVwHoVFL/foqC8HS3EacBAM8bsu+Trz9MDE//lFV+KfL70W519+Iy66sr/64A59eCfpD/AQD7gfDm+//XbU19fj2WefdUHvArz22mvRv39/dQKQREsqnqpv8uzwpfYTSnweaCmhIb4hfhILBBO/mr6PT8QfN26c+gUceiUYY+DAgbjvvvtK5V+n1StK/GKXIX5lhviG+LVC/E5jbEwdG+LzTbwJS7phT4LYYTKrccePiX+dJsYQ3xC+agnPC4Ihfvzrg0t8+uRSpTBHfXPUZ7LGGTLxzVt241sAFPHjEkcTZGBskIQPdMZPScfFi2qUEyvxu/LPGJuxdf7PVJsf1IhvCYn9t/Pkaj99+nT1G2f0/036zTMDY4M4fMD8dl7lp0pr7vIcksJHi7/CW9kFeGXqBwbGBrH6APlVUn5bC3KteU2bkBQavliLt2cvNDA2SMQHkvLbWpBrLVixGQbGBsYHassHrIUrv4GBsYHxgdryAWvR6q0wMDYwPlBbPvD/GKtYMhaHLUMAAAAASUVORK5CYII=[/img]使用AT32F413RCT7在仿真时，system viewer是空的，请问怎么才能显示呢

如题

[color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]选择 5 位数码管做显示，实现 5 种倒[/size][/font][/backcolor][/color][color=rgb(65, 131, 196)][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]计时[/size][/font][/backcolor][/color][color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]模式，通过控制按键进行选择[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]1、99999s-0s[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]2、9999s-0s[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]3、999s-0s[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]4、99s-0s[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]5、9s-0s[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]6、开始值由[/size][/font][/backcolor][/color][color=rgb(65, 131, 196)][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]人工[/size][/font][/backcolor][/color][color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]输入-0s[/size][/font][/backcolor][/color] [color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]求c程序及[/size][/font][/backcolor][/color][color=rgb(65, 131, 196)][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]仿真[/size][/font][/backcolor][/color][color=#333333][backcolor=rgb(255, 255, 255)][font=微软雅黑][size=16px]图[/size][/font][/backcolor][/color]

[color=#444444][backcolor=rgb(222, 240, 251)][font=Tahoma, "][size=16px]两条线之间的寄生电容，可以计算[/size][/font][/backcolor][/color] [color=#444444][backcolor=rgb(222, 240, 251)][font=Tahoma, "][size=16px]某条线的寄生电容，cadence可以直接查看到。[/size][/font][/backcolor][/color] [color=#444444][backcolor=rgb(222, 240, 251)][font=Tahoma, "][size=16px]问题：[/size][/font][/backcolor][/color][color=#444444][backcolor=rgb(222, 240, 251)][font=Tahoma, "][size=16px]1、pcb板如果有多条线，（分布有规律或者分布无规律），想知道某些点之间的寄生电容值[/size][/font][/backcolor][/color] 2、如果有一个复杂的电容网络拓扑，测量任意两个点之间的电容 [color=#444444][backcolor=rgb(222, 240, 251)][font=Tahoma, "][size=16px]哪个软件可以完成这个任务呢，谢谢大家[/size][/font][/backcolor][/color]

能够正常烧录程序，调试时，出现如下错误，是什么情况。Fatal error: 0xc04 The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.

CH32F103 的USB有没有仿真CH340的例程？

仿真器可以做外部中断仿真吗？

proteus，还是什么软件，里面是否有航顺的单片机？

SH79F085X 只能用JATG 口仿真吗？

在自己的设计中调用Quartusii生成的firIP核，我的设计是verilg，fir的顶层是verilog，功能实现全是vhdl。然后在modelsim中进行仿真，仿真时提示错误Instantiation of 'fir_top_0002' failed.quartus版本是13.0 modelsim版本是 modelsim_altera 10.1d 百度也查不到。。求助高手。。

[i=s] 本帖最后由 yydianzi 于 2020-8-26 16:27 编辑 [/i] [img]C:\Users\Administrator\Desktop\1.png[/img]

新手一枚，求教用LEIL如何创建SAMD20工程，以及下载、仿真配置。