问答

使用了HC32F460PETB单片机，在批量生产中个别产品出现串口乱码情况，经排查是硬件电路设计为外部8M有源晶振，代码中en_clk_xtal_mode配置的是CLKXtalModeOsc = 1u，后将代码配置修改为CLKXtalModeExtclk =1u后串口打印正常，有大神能帮忙解释下原理吗？ 为什么这个地方配置错误，产品会出现问题，之前小批量生产的时候没有出现乱码现象。

如题所述

在使用AVR单片机时，发现设置MAIN时钟时需要对CCP寄存器进行解锁操作（4个内指令完成）。在查看了protected_io.S文件后，发现此使用了汇编来解锁以保证能在4个指令周期内完成时钟配置。但是有一个疑问就是，调用protected_write_io函数来操作CCP寄存器时，汇编代码中使用的寄存器为R20和R24为什么不是其他寄存器呢？#include PUBLIC_FUNCTION(protected_write_io) #if defined(__GNUC__) #ifdef RAMPZ out _SFR_IO_ADDR(RAMPZ), r1 // Clear bits 23:16 of Z #endif //为什么使用R24和R22以及R20，为什么不能是其他寄存器。这些寄存器都是protected_write_io函数的形参 [color=#f00000]movw r30, r24 [/color] // Load addr into Z [color=#f00000]out CCP, r22 [/color] // Start CCP handshake [color=#f00000]st Z, r20 [/color] // Write value to I/O register [color=#f00000]ret[/color] // Return to caller #elif defined(__IAR_SYSTEMS_ASM__) # if !defined(CONFIG_MEMORY_MODEL_TINY) && !defined(CONFIG_MEMORY_MODEL_SMALL) \ && !defined(CONFIG_MEMORY_MODEL_LARGE) # define CONFIG_MEMORY_MODEL_SMALL # endif # if defined(CONFIG_MEMORY_MODEL_LARGE) ldi r20, 0 out RAMPZ, r20 // Reset bits 23:16 of Z movw r30, r16 // Load addr into Z # elif defined(CONFIG_MEMORY_MODEL_TINY) ldi r31, 0 // Reset bits 8:15 of Z mov r30, r16 // Load addr into Z # else movw r30, r16 // Load addr into Z # endif # if defined(CONFIG_MEMORY_MODEL_TINY) out CCP, r17 // Start CCP handshake st Z, r18 // Write value to I/O register # elif defined(CONFIG_MEMORY_MODEL_SMALL) out CCP, r18 // Start CCP handshake st Z, r19 // Write value to I/O register # elif defined(CONFIG_MEMORY_MODEL_LARGE) out CCP, r19 // Start CCP handshake st Z, r20 // Write value to I/O register # else # error Unknown memory model in use, no idea how registers should be accessed # endif ret #else # error Unknown assembler #endif END_FUNC(protected_write_io) END_FILE()

我在配置HC32F460的时钟，遇到了一个比较鬼畜的问题。我按照如下代码设置了时钟，但奇怪的是，我在硬件上端接晶振引脚，按说芯片会宕机才对，但芯片居然毫无影响，继续运行。想麻烦大家帮我看看，是我哪里设置的不对 [color=#d4d4d4][backcolor=rgb(30, 30, 30)][font=Menlo, Monaco, "][size=12px] [color=#569cd6]void[/color] [color=#dcdcaa]SystemClk_Init[/color]([color=#569cd6]void[/color]) { [color=#4ec9b0]stc_clk_sysclk_cfg_t[/color] [color=#9cdcfe]stcSysClkCfg[/color]; [color=#4ec9b0]stc_clk_xtal_cfg_t[/color] [color=#9cdcfe]stcXtalCfg[/color]; [color=#4ec9b0]stc_clk_mpll_cfg_t[/color] [color=#9cdcfe]stcMpllCfg[/color]; [color=#569cd6]MEM_ZERO_STRUCT[/color]([color=#9cdcfe]stcSysClkCfg[/color]); [color=#569cd6]MEM_ZERO_STRUCT[/color]([color=#9cdcfe]stcXtalCfg[/color]); [color=#569cd6]MEM_ZERO_STRUCT[/color]([color=#9cdcfe]stcMpllCfg[/color]); [color=#6a9955]/* Set bus clk div. */[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enHclkDiv[/color] = [color=#4fc1ff]ClkSysclkDiv1[/color]; [color=#6a9955]// 168MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enExclkDiv[/color] = [color=#4fc1ff]ClkSysclkDiv2[/color]; [color=#6a9955]// 84MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk0Div[/color] = [color=#4fc1ff]ClkSysclkDiv1[/color]; [color=#6a9955]// 168MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk1Div[/color] = [color=#4fc1ff]ClkSysclkDiv2[/color]; [color=#6a9955]// 84MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk2Div[/color] = [color=#4fc1ff]ClkSysclkDiv4[/color]; [color=#6a9955]// 42MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk3Div[/color] = [color=#4fc1ff]ClkSysclkDiv4[/color]; [color=#6a9955]// 42MHz[/color] [color=#9cdcfe]stcSysClkCfg[/color].[color=#9cdcfe]enPclk4Div[/color] = [color=#4fc1ff]ClkSysclkDiv2[/color]; [color=#6a9955]// 84MHz[/color] [color=#dcdcaa]CLK_SysClkConfig[/color](&[color=#9cdcfe]stcSysClkCfg[/color]); [color=#6a9955]/* Switch system clock source to MPLL. */[/color] [color=#6a9955]/* Use Xtal as MPLL source. */[/color] [color=#9cdcfe]stcXtalCfg[/color].[color=#9cdcfe]enMode[/color] = [color=#4fc1ff]ClkXtalModeOsc[/color]; [color=#9cdcfe]stcXtalCfg[/color].[color=#9cdcfe]enDrv[/color] = [color=#4fc1ff]ClkXtalLowDrv[/color]; [color=#9cdcfe]stcXtalCfg[/color].[color=#9cdcfe]enFastStartup[/color] = [color=#4fc1ff]Disable[/color]; [color=#dcdcaa]CLK_XtalConfig[/color](&[color=#9cdcfe]stcXtalCfg[/color]); [color=#dcdcaa]CLK_XtalCmd[/color]([color=#4fc1ff]Enable[/color]); [color=#6a9955]/* MPLL config. */[/color] [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]pllmDiv[/color] = [color=#b5cea8]1u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]plln[/color] = [color=#b5cea8]42u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]PllpDiv[/color] = [color=#b5cea8]2u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]PllqDiv[/color] = [color=#b5cea8]2u[/color]; [color=#9cdcfe]stcMpllCfg[/color].[color=#9cdcfe]PllrDiv[/color] = [color=#b5cea8]2u[/color]; [color=#dcdcaa]CLK_SetPllSource[/color]([color=#4fc1ff]ClkPllSrcXTAL[/color]); [color=#dcdcaa]CLK_MpllConfig[/color](&[color=#9cdcfe]stcMpllCfg[/color]); [color=#6a9955]/* flash read wait cycle setting */[/color] [color=#dcdcaa]EFM_Unlock[/color](); [color=#dcdcaa]EFM_SetLatency[/color]([color=#569cd6]EFM_LATENCY_4[/color]); [color=#dcdcaa]EFM_Lock[/color](); [color=#6a9955]/* Enable MPLL. */[/color] [color=#dcdcaa]CLK_MpllCmd[/color]([color=#4fc1ff]Enable[/color]); [color=#6a9955]/* Wait MPLL ready. */[/color] [color=#c586c0]while[/color] ([color=#4fc1ff]Set[/color] != [color=#dcdcaa]CLK_GetFlagStatus[/color]([color=#4fc1ff]ClkFlagMPLLRdy[/color])) { } [color=#6a9955]/* Switch system clock source to MPLL. */[/color] [color=#dcdcaa]CLK_SetSysClkSource[/color]([color=#4fc1ff]ClkSysSrcXTAL[/color]); } [/size][/font][/backcolor][/color]

请问HK32F031默认使用HSI 8M时钟作为sysclk， 我想使用HSI56作为系统时钟应该怎么配置？我设置了 RCC_CFGR4（0x400210e8）bit7 ESSS=1, bit[2:0] ESW=010, 但是没有任何效果。 HK32F0xx的库文件中也没有RCC_CFGR4相关的任何定义与描述。 另外，论坛中有HK32F030M的示例程序，那有没有HK32F031的示例程序呢？ 望解惑，谢谢！