fpga程序问题赏100家园币

feiyang07252025-03-03

   always @(posedge sys_clk0 ) begin
   s1 <= clk_init;  //CLK_pwm
s2 <= s1;    //0
   end
   assign pose_sclk=!s2&s1; //
  always @(posedge sys_clk0 or negedge rst_n)
if(~rst_n) begin
   rst_n<=1'b1;
clk_100m<=1'b0;
   state_d<=WAIT;
end
else begin if(pose_sclk) // 上升沿
   state_d<=A;
else case(state_d)  //0
   A:begin
clk_100m<=1'b1;
state_d<=B;
end
   B:begin
clk_100m<=1'b0;
state_d<=WAIT;
end
   WAIT:begin
clk_100m<=1'b0;
end
   default: state_d <= WAIT;
endcase
   end

   always @(posedge sys_clk0 ) begin
   s1 <= clk_init;  //CLK_pwm
s2 <= s1;    //0
   end
   assign pose_sclk=!s2&s1; //
  always @(posedge sys_clk0 or negedge rst_n)
if(~rst_n) begin
   rst_n<=1'b1;
clk_100m<=1'b0;
   state_d<=WAIT;
end
else begin if(pose_sclk) // 上升沿
   state_d<=A;
else case(state_d)  //0
   A:begin
clk_100m<=1'b1;
state_d<=B;
end
   B:begin
clk_100m<=1'b0;
state_d<=WAIT;
end
   WAIT:begin
clk_100m<=1'b0;
end
   default: state_d <= WAIT;
endcase
   end
always @(posedge sys_clk0 ) begin
   s1 <= clk_init;  //CLK_pwm
            s2 <= s1;    //0
      end
   assign pose_sclk=!s2&s1; //
  always @(posedge sys_clk0 or negedge rst_n)
if(~rst_n) begin
         rst_n<=1'b1;
            clk_100m<=1'b0;
   state_d<=WAIT;
            end
else begin if(pose_sclk) // 上升沿
   state_d<=A;
else case(state_d)  //0
   A:begin
            clk_100m<=1'b1;
            state_d<=B;
            end
   B:begin
            clk_100m<=1'b0;
            state_d<=WAIT;
            end
   WAIT:begin
            clk_100m<=1'b0;
            end
   default: state_d <= F;
endcase
      end
50Mhz晶振，sys_clk0 倍频100Mhz，clk_init作为输入脉冲信号1Khz-100Khz。在clk_init上升沿输出clk_100m高低变化一次。发现clk_100m有抖动。

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entropyhdl

没仔细看，你这一段式看着好累，怎么觉得你这到wait状态不复位就不动了啊，哪来的100M时钟，另外，搞上升沿下检验用S1S2=01，或=10来判断比较直观，可靠点多拍几次，比如S3S2S1S0=1100 或=0011来判断，还可以调整位置

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2025-03-03

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