TI VC5509A 用DMA向MCBSP0发送时只进入一次FRAME中断，然后再也不进入中断了？

只看该作者 · 2015-7-13 10:43

芯片是VC5509A ,用DMA向MCBSP0发送时，只有在仿真开始的时候进入一次中断，然后再也没有进入过，很奇怪！

//DMA发送部分：

/* Create DMA Receive Side Configuration */
DMA_Config dmaConfig3 = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_DARAM,
DMA_DMACSDP_DATATYPE_32BIT//一个element有4个byte
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_POSTINC,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_REPEAT_ON,
DMA_DMACCR_AUTOINIT_ON,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_FRAME,
DMA_DMACCR_SYNC_XEVT0
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
0, /* DMACSSAL */
0, /* DMACSSAU */
0, /* DMACDSAL */
0, /* DMACDSAU */
Mcbsp1N, /* DMACEN */// 一个fram有N 个32bit的element
1, /* DMACFN *///一个block有1个fram
0, /* DMACFI */
0, /* DMACEI */
};

//中断函数

volatile Uint16 csr;
//---------Function prototypes---------
interrupt void DMA3Isr(void)
{
csr=DMA_RGETH(mhDma3,DMACSR);
}
#endif

void DMAtaskFxn(void);

#pragma DATA_SECTION(XmtPort,"dmaMem")
Uint32 XmtPort[Mcbsp1N];

void CS4351DMAtaskFxn(void)
{

Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;

Data32Set(XmtPort,0,Mcbsp1N);

/* By default, the TMS320C55xx compiler assigns all data symbols word */
/* addresses. The DMA however, expects all addresses to be byte */
/* addresses. Therefore, we must shift the address by 2 in order to */
/* change the word address to a byte address for the DMA transfer. */
hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);

dstAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR_H(hMcbsp0,DXR1))) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR_H(hMcbsp0,DXR1))) << 1) & 0xFFFFu;
srcAddrHi = (Uint16)(((Uint32)(&XmtPort)) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(&XmtPort)) << 1) & 0xFFFFu;

dmaConfig3.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaConfig3.dmacssau = srcAddrHi;
dmaConfig3.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaConfig3.dmacdsau = dstAddrHi;

mhDma3 = DMA_open(DMA_CHA3,DMA_OPEN_RESET);
DMA3xmtEventId = DMA_getEventId( mhDma3 );
IRQ_clear(DMA3xmtEventId);
IRQ_enable(DMA3xmtEventId);
IRQ_plug(DMA3xmtEventId,&DMA3Isr);
MCBSP_config(hMcbsp0, &Mcbsp_config0);
DMA_config(mhDma3,&dmaConfig3);
delay_ms(1);
MCBSP_start(hMcbsp0, MCBSP_SRGR_START|MCBSP_XMIT_START|MCBSP_SRGR_FRAMESYNC,0X300U);

/* Prime MCBSP DXR */
while (!(MCBSP_xrdy(hMcbsp0))){
;
}
MCBSP_write32(hMcbsp0,XmtPort[0]);

DMA_start(mhDma3);

DMA_getConfig(mhDma3,&dmaTESTConfig3);

}