程序在编译时出现error（10346）：formal port or pamrameter“clk“must have actual or default vale error（10784）：see declaration for object ”clk“的错误，程序如下：LIBRARY ieee;
USE ieee. std_logic_1164.all;
USE ieee. std_logic_unsigned.all;
ENTITY butterfly IS
PORT (clk, start : IN STD_LOGIC;
in1_re, in1_im, in2_re, in2_im : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
w_re, w_im : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
out1_re, out1_im, out2_re, out2_im : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END butterfly;
ARCHITECTURE struc OF butterfly IS
COMPONENT sub8b
PORT (din: IN STD_LOGIC;
a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
d: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
dout: OUT STD_LOGIC);
END COMPONENT;
COMPONENT adder8b
PORT(cin: IN STD_LOGIC;
a , b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cout:OUT STD_LOGIC);
END COMPONENT;
COMPONENT multi8
PORT(clk, start:IN STD_LOGIC;
a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ariend:OUT STD_LOGIC;
dout:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT;
COMPONENT enable
PORT(clk, d:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
enout:OUT STD_LOGIC);
END COMPONENT;
SIGNAL temp_re, temp_im: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL temp1, temp2, tem1, tem2: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Y1_RE, Y1_IM, Y2_RE, Y2_IM: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL W:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL gnd, startup1, startup2, rstart1, rstart2:STD_LOGIC;
BEGIN
out1_re<=Y1_RE;
out1_im<=Y1_IM;
out2_re<=Y2_RE;
out2_im<=Y2_IM;
Q1:multi8 PORT MAP(clk=>clk,start=>start,a=>in2_re,b=>w_re,ariend=>startup1,dout=>temp_re);
Q2:multi8 PORT MAP(clk=>clk,start=>start,a=>in2_im,b=>w_im,ariend=>startup2,dout=>temp_im);
Q3:adder8b PORT MAP(cin=>startup1,a=>temp_re(14 DOWNTO 7),b=>temp_im(14
DOWNTO 7),s=>temp2);
Q4:sub8b PORT MAP(din=>startup2, a=>temp_re(14 DOWNTO 7),b=>temp_im(14
DOWNTO 7),d=>temp1);
Q5:enable PORT MAP(d=>temp1,data=>tem1, enout=>rstart1);
Q6:enable PORT MAP(d=>temp2,data=>tem2, enout=>rstart2);
Q7:sub8b PORT MAP(din=>rstart1,a=>in1_re,b=>temp1,d=>Y2_RE);
Q8:sub8b PORT MAP(din=>rstart2,a=>in1_im,b=>temp2,d=>Y2_IM);
Q9:adder8b PORT MAP(cin=>rstart1,a=>in1_re,b=>temp1,s=>Y1_RE);
Q10:adder8b PORT MAP(cin=>rstart2,a=>in1_im,b=>temp2,s=>Y1_IM);
END; |
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