Clock Configuration Reset State In reset state, the RCCU_CFR value is 8008h and The PCU_MDIVR and PCU_PDIVR register values (FACT bits) are 0000h. Consequently, in reset state the clock configuration is DIV2 = 1, CK2_16=1 and therefore MCLK, PCLK1 and PCLK2 operate at half the external clock frequency CLK
楼主
标题置顶
标题高亮
