FPGA 控制 NOR FLASH

只看该作者 · 2015-8-26 21:44

最近在搞一个项目。到了存储部分卡了2个月了。
FLASH 用的是 AM29DL640H-90E
FPGA 用的是 EP4CE115F23I7
有谁这样子玩过？用VERILOG 写的读写 NOR FLASH 的程序。
网上的资料小得可怜。

只看该作者 · 2015-8-26 21:49

板子也搞好了。。。
程序也写得差不多了，就储存。郁闷啊。。。在淘宝上问了好多卖开发板的人，大多都没搞过。都说用NIOS自动配置。
如果用NIOS 不如用个ARM+FPGA。。
哎，**全部跑 FPGA。。看看万能的网络这次行不行啦。。真的就没有高手么？
自己先顶一下。。。

只看该作者 · 2015-8-26 21:55

module FLASH_TEST(
sys_clk,
sys_rst_n,
LED,
FLASH_ADDR,
FLASH_DQ,
FLASH_CE,
FLASH_OE,
FLASH_WE,
FLASH_RST

);
input sys_clk;
input sys_rst_n;

output [7:0]LED;
output [20:0]FLASH_ADDR;
inout [15:0]FLASH_DQ;
output FLASH_CE;
output FLASH_OE;
output FLASH_WE;
output FLASH_RST;

//####################-----------状态机频率---FLASH用---我的FLASH是90ns的---状态机用100ns即频率为10M#################
reg [15:0]clk_flash_10m;
reg clk_10m;
always @(posedge sys_clk)
begin
if(clk_flash_10m==16'd5)
begin
clk_flash_10m=0;clk_10m=1;
end
else
begin
clk_flash_10m=clk_flash_10m+1;clk_10m=0;
end
end
//####################-----------状态机频率---FLASH用------#################

assign FLASH_CE = 1'b0;
assign FLASH_RST = 1'b1;

reg [7:0] state;//state

reg FLASH_OE; // flash output signal
reg FLASH_WE;
reg [20:0] FLASH_ADDR;//flash address
reg [15:0]FLASH_DQ;
reg [15:0]FLASH_DQ_TEM;
reg [7:0] LED;//led,compare the writed data with the readed data offlash.
//if the first writed data is samed with the firstreader data, ledr[0]=0.
//if the second writed data is samed with thesecond reader data ,ledr[1]=0
//if erase chip succeed,ledr[2]=0;

reg [39:0] erase_cnt; //chip erase hold time
reg [15:0] number_flash;
always@ (posedge clk_10m or negedge sys_rst_n)
begin
if(!sys_rst_n)  //reset
begin
state <= 99;
LED <= 8'd0;             // led of red off
FLASH_OE <= 1'b1;       // output enable lose effective
FLASH_WE<=1;
FLASH_ADDR <= 21'h555;

erase_cnt <= 40'd0;
number_flash<=0;
FLASH_DQ_TEM<=0;

end
else
begin
case(state)
// chip erase初始化/格式化
99: begin if(number_flash==3000)begin state <= 0; number_flash<=0;end else begin number_flash<=number_flash+1;end end
0:  begin FLASH_ADDR <= 21'h555; state <= 1  ;end
1:  begin FLASH_WE <= 0;FLASH_DQ <= 16'haa; state <= 2  ;end
2:  begin FLASH_WE <= 1;if(number_flash==1)begin state <= 3; number_flash<=0;end else begin number_flash<=number_flash+1;end end
3:  begin FLASH_ADDR <= 21'h2aa; state <= 4  ;end
4:  begin FLASH_WE <= 0;FLASH_DQ <= 16'h55; state <= 5  ;end
5:  begin FLASH_WE <= 1;if(number_flash==1)begin state <= 6; number_flash<=0;end else begin number_flash<=number_flash+1; end end
6:  begin FLASH_ADDR <= 21'h555; state <= 7  ;end
7:  begin FLASH_WE <= 0;FLASH_DQ <= 16'h80; state <= 8  ;end
8:  begin FLASH_WE <= 1;if(number_flash==1)begin state <= 9; number_flash<=0;end else begin number_flash<=number_flash+1; end end
9:  begin FLASH_ADDR <= 21'h555; state <= 10 ;end
10: begin FLASH_WE <= 0;FLASH_DQ <= 16'haa; state <= 11 ;end
11: begin FLASH_WE <= 1;if(number_flash==1)begin state <= 12;number_flash<=0;end else begin number_flash<=number_flash+1;end end
12: begin FLASH_ADDR <= 21'h2aa; state <= 13 ;end
13: begin FLASH_WE <= 0;FLASH_DQ <= 16'h55; state <= 14 ;end
14: begin FLASH_WE <= 1;if(number_flash==1)begin state <= 15;number_flash<=0;end else begin number_flash<=number_flash+1;end end
15: begin FLASH_ADDR <= 21'b0000_0100_0000_0000_0000_0; state <= 16 ;end//扇区擦除命令
16: begin FLASH_WE <= 0; FLASH_DQ <= 16'h30; state <= 17 ;end
17: begin FLASH_WE <= 1;if(number_flash==1)begin state <= 18;number_flash<=0;end else begin number_flash<=number_flash+1;end end
18: begin // FLASH 初始化，0.7s一个扇区
if(erase_cnt == 40'd100000000)
begin
state <= 19;
//LED[0]<=1;//初始化完成 LED提示
end
else
begin
state <= 18;  // current state
erase_cnt <= erase_cnt + 1'b1;
end
end
//**********************write first data**********************
19 : begin FLASH_ADDR <= 21'h555; state <= 20 ;end
20 : begin FLASH_WE <= 0; FLASH_DQ <= 16'haa; state <= 21 ;end
21 : begin FLASH_WE <= 1;if(number_flash==1)begin  state <= 22;number_flash<=0;end else begin number_flash<=number_flash+1;end end
22 : begin FLASH_ADDR <= 21'h2aa; state <= 23 ;end
23 : begin FLASH_WE <= 0;FLASH_DQ <= 16'h55; state <= 24 ;end
24 : begin FLASH_WE <= 1;if(number_flash==1)begin  state <= 25;number_flash<=0;end else begin number_flash<=number_flash+1;end end
25 : begin FLASH_ADDR <= 21'h555; state <= 26 ;end
26 : begin FLASH_WE <= 0;FLASH_DQ <= 16'ha0; state <= 27 ;end
27 : begin FLASH_WE <= 1;if(number_flash==1)begin  state <= 28;number_flash<=0;end else begin number_flash<=number_flash+1;end end
28 : begin FLASH_ADDR <= 21'h008000;    state <= 29; end//FIRST_ADDR = 0 ; FIRST_DATA = 1;16'h01
29 : begin FLASH_WE <= 0;FLASH_DQ <= 16'haaaa; state <= 30 ;end
30 : begin FLASH_WE <= 1;if(number_flash==90)begin  state <= 31;number_flash<=0;end else begin number_flash<=number_flash+1;end end
31 : begin state <= 32;       end

//********************** write second data **************************
32 : begin FLASH_ADDR <= 21'h555; state <= 33 ;end
33 : begin FLASH_WE <= 0;FLASH_DQ <= 16'haa; state <= 34 ;end
34 : begin FLASH_WE <= 1;if(number_flash==1)begin  state <= 35;number_flash<=0;end else begin number_flash<=number_flash+1;end end
35 : begin FLASH_ADDR <= 21'h2aa; state <= 36 ;end
36 : begin FLASH_WE <= 0;FLASH_DQ <= 16'h55; state <= 37 ;end
37 : begin FLASH_WE <= 1;if(number_flash==1)begin  state <= 38;number_flash<=0;end else begin number_flash<=number_flash+1;end end
38 : begin FLASH_ADDR <= 21'h555; state <= 39 ;end
39 : begin FLASH_WE <= 0;FLASH_DQ <= 16'ha0; state <= 40 ;end
40 : begin FLASH_WE <= 1;if(number_flash==1)begin  state <= 41;number_flash<=0;end else begin number_flash<=number_flash+1;end end
// write 16'h02 of data to 21'h1 of address
41 : begin FLASH_ADDR <= 21'h008001;  state <= 42;end
42 : begin FLASH_WE <= 0;FLASH_DQ <= 16'h0; state <= 43 ;end
43 : begin FLASH_WE <= 1;if(number_flash==90)begin  state <= 44;number_flash<=0;end else begin number_flash<=number_flash+1;end end
44 : begin state <= 45;             end

45 : begin FLASH_ADDR <= 21'h008000; state <= 46; end
46 : begin FLASH_OE <= 0; state <= 47 ;end
47 : begin FLASH_DQ_TEM <= FLASH_DQ; state <= 48 ;end
48 : begin FLASH_OE <= 1; state <= 49 ;end

      49 : begin
state <= 50;
LED[0] <= FLASH_DQ_TEM[0];
LED[1] <= FLASH_DQ_TEM[1];
LED[2] <= FLASH_DQ_TEM[2];
LED[3] <= FLASH_DQ_TEM[3];
LED[4] <= 1;
LED[5] <= 1;
LED[6] <= 1;
LED[7] <= 1;

            end
      50: begin  end

            default : state <= 50;
         endcase
      end
end

endmodule