RCC_Configuration();
/* NVIC configuration */
NVIC_Configuration();
/* Configure the GPIO ports */
GPIO_Configuration();
/* Configure the DMA */
//DMA_Configuration();
/* DMA Channel4 (triggered by USART1 Tx event) Config */
DMA_DeInit(DMA1_Channel4);
DMA_InitStructure.DMA_PeripheralBaseAddr = USART1_DR_Base;
DMA_InitStructure.DMA_MemoryBaseAddr = (u32)TxBuffer1;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = TxBufferSize1;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA1_Channel4, &DMA_InitStructure);
DMA_DeInit(DMA1_Channel5);
DMA_InitStructure1.DMA_PeripheralBaseAddr = USART1_DR_Base;
DMA_InitStructure1.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure1.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure1.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure1.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure1.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure1.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure1.DMA_M2M = DMA_M2M_Disable;
DMA_InitStructure1.DMA_MemoryBaseAddr = (u32)&RxBuffer[0];
DMA_InitStructure1.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure1.DMA_BufferSize = 4;
DMA_Init(DMA1_Channel5, &DMA_InitStructure1);
SetupUSART();
/* Enable USART1 DMA TX request */
USART_DMACmd(USART1, USART_DMAReq_Tx|USART_DMAReq_Rx, ENABLE);
/* Enable DMA Channel5 Transfer Complete interrupt */
DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
/* Enable the USART1 Receive Interrupt */
//USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
/* Enable DMA Channel4 */
//DMA_Cmd(DMA1_Channel4, ENABLE);
/* Enable DMA Channel5 */
DMA_Cmd(DMA1_Channel5, ENABLE);
CurrDataCounter_End = DMA_GetCurrDataCounter(DMA1_Channel5);
/* Wait until DMA_Channel 4 Transfer Complete */
while(1)
{
；
}
void DMAChannel5_IRQHandler(void)
{
if(DMA_GetITStatus(DMA1_IT_TC5))
{
DMA_ClearITPendingBit(DMA1_IT_GL5);
//CurrDataCounter_End = DMA_GetCurrDataCounter(DMA1_Channel5);
DMA_Cmd(DMA1_Channel5, DISABLE);
DMA_DeInit(DMA1_Channel5);
DMA_Init(DMA1_Channel5, &DMA_InitStructure1);
/* Enable DMA Channel5 Transfer Complete interrupt */
DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
DMA_Cmd(DMA1_Channel5, ENABLE);
DMA_ClearITPendingBit(DMA1_IT_GL5);
dmaflag = 1;
for(i=0;i<5;i++)
RxBuffer1=0;
}
}
|
楼主
