最近开始用VHDL 写程序，定义了一个输出端口filter_out
ENTITY f_Current_A IS
PORT( clk : IN std_logic;
clk2 : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
filter_in : IN std_logic_vector(15 DOWNTO 0); --
filter_out : out std_logic_vector(15 DOWNTO 0)
);
END f_Current_A;
在程序process外用一个整型量tEmp给filter_out 赋值时永远有错误，无论把tEmp的数据类型改成何种，filter_out类型改成何种，编译时都有错误，万分沮丧；求高人指点；具体错误为ERROR - CD371 :"E:\filter_design\iir_selfwrite.vhd":177:16:177:37|No matching overload for conv_std_logic_vector；
赋值语句为
...................................
END PROCESS Output_process2;
filter_out <= "0000000000000000";
filter_out <= CONV_STD_LOGIC_VECTOR(tEmp);
只用filter_out <= "0000000000000000";倒是没有问题
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