/******************************************************************************
* @file main.c
* @version V2.00
* $Revision: 8 $
* $Date: 14/08/05 11:13a $
* @brief
* Demonstrate SPI master loop back transfer.
* This sample code needs to connect SPI0_MISO0 pin and SPI0_MOSI0 pin together.
* It will compare the received data with transmitted data.
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include <stdio.h>
#include "NUC123.h"
#define TEST_COUNT 64
uint32_t g_au32SourceData[TEST_COUNT];
uint32_t g_au32DestinationData[TEST_COUNT];
volatile uint32_t PDMA_TEST_LENGTH = 64;
volatile uint8_t SrcArray[64];
volatile uint8_t DestArray[64];
uint32_t volatile u32IsTestOver = 0xFF;
/* Function prototype declaration */
void SYS_Init(void);
void SPI_Init(void);
#define DMA_SPI1_TX 2
#define DMA_SPI1_RX 3
unsigned char temp;
/* ------------- */
/* Main function */
/* ------------- */
int main(void)
{
int i;
/* Unlock protected registers */
SYS_UnlockReg();
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Configure UART0: 115200, 8-bit word, no parity bit, 1 stop bit. */
UART_Open(UART0, 115200);
for (i=0;i<64;i++)
{
SrcArray=i;
DestArray=0;
}
GPIO_SetMode(PA, BIT14, GPIO_PMD_OUTPUT);
/* Init SPI */
SPI_Init();
SPI1->CNTRL |= SPI_CNTRL_FIFO_Msk;
PDMA_Open(1 << DMA_SPI1_TX);
PDMA_SetTransferCnt(DMA_SPI1_TX, PDMA_WIDTH_8, PDMA_TEST_LENGTH);
PDMA_SetTransferAddr(DMA_SPI1_TX, (uint32_t)SrcArray, PDMA_SAR_INC, (uint32_t)&SPI1->TX[0], PDMA_DAR_FIX);
PDMA_EnableInt(DMA_SPI1_TX, PDMA_IER_BLKD_IE_Msk);
PDMA2->CSR = (PDMA2->CSR & ~(PDMA_CSR_MODE_SEL_Msk) | (0x2 << PDMA_CSR_MODE_SEL_Pos));
PDMA_Open(1 << DMA_SPI1_RX);
PDMA_SetTransferCnt(DMA_SPI1_RX, PDMA_WIDTH_8, PDMA_TEST_LENGTH);
PDMA_SetTransferAddr(DMA_SPI1_RX, (uint32_t)&SPI1->RX[0], PDMA_SAR_FIX, (uint32_t)DestArray, PDMA_DAR_INC);
PDMA_EnableInt(DMA_SPI1_RX, PDMA_IER_BLKD_IE_Msk);
PDMA3->CSR = (PDMA3->CSR & ~(PDMA_CSR_MODE_SEL_Msk) | (0x1 << PDMA_CSR_MODE_SEL_Pos));
PDMA_GCR->PDSSR0=0x0FF2301;
NVIC_EnableIRQ(PDMA_IRQn);
SPI_TRIGGER_RX_PDMA(SPI1);
SPI_TRIGGER_TX_PDMA(SPI1);
PDMA_Trigger(DMA_SPI1_RX);
PDMA_Trigger(DMA_SPI1_TX);
PA14=0;
while(1)
{
if(PA14==1)
{
for(i=0;i<64;i++)
{
if(SrcArray!=DestArray)
while(1);
SrcArray=i;
DestArray=0;
}
SPI_TRIGGER_RX_PDMA(SPI1);
SPI_TRIGGER_TX_PDMA(SPI1);
PDMA_Trigger(DMA_SPI1_RX);
PDMA_Trigger(DMA_SPI1_TX);
PA14=0;
}
}
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable XT1_OUT (PF0) and XT1_IN (PF1) */
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
/* Enable external 12MHz XTAL */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_CLKDIV_HCLK(1));
/* Select HXT as the clock source of UART0 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Select HCLK as the clock source of SPI0 */
CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL1_SPI1_S_HCLK, MODULE_NoMsk);
/* Enable UART peripheral clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable SPI0 peripheral clock */
CLK_EnableModuleClock(SPI1_MODULE);
/* Enable PDMA module clock */
CLK->AHBCLK |= CLK_AHBCLK_PDMA_EN_Msk;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD;
/* Setup SPI0 multi-function pins */
SYS->GPC_MFP = SYS_GPC_MFP_PC8_SPI1_SS0 | SYS_GPC_MFP_PC9_SPI1_CLK | SYS_GPC_MFP_PC10_SPI1_MISO0 | SYS_GPC_MFP_PC11_SPI1_MOSI0;
SYS->ALT_MFP = SYS_ALT_MFP_PC8_SPI1_SS0 | SYS_ALT_MFP_PC9_SPI1_CLK | SYS_ALT_MFP_PC10_SPI1_MISO0 | SYS_ALT_MFP_PC11_SPI1_MOSI0;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and CyclesPerUs automatically. */
SystemCoreClockUpdate();
}
void SPI_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init SPI */
/*---------------------------------------------------------------------------------------------------------*/
/* Configure as a master, clock idle low, 32-bit transaction, drive output on falling clock edge and latch input on rising edge. */
/* Set IP clock divider. SPI clock rate = 2MHz */
SPI_Open(SPI1, SPI_SLAVE, SPI_MODE_0, 8, 36000000);
/* Enable the automatic hardware slave select function. Select the SS pin and configure as low-active. */
SPI_EnableAutoSS(SPI1, SPI_SS0, SPI_SS_ACTIVE_LOW);
}
void PDMA_IRQHandler(void)
{
uint32_t status = PDMA_GET_INT_STATUS();
if(status & 0x1) /* CH0 */
{
if(PDMA_GET_CH_INT_STS(0) & 0x2)
PDMA_CLR_CH_INT_FLAG(0, PDMA_ISR_BLKD_IF_Msk);
}
else if(status & 0x2) /* CH1 */
{
if(PDMA_GET_CH_INT_STS(1) & 0x2)
PDMA_CLR_CH_INT_FLAG(1, PDMA_ISR_BLKD_IF_Msk);
}
else if(status & 0x4) /* CH2 */
{
if(PDMA_GET_CH_INT_STS(2) & 0x2)
PA14=1;
PDMA_CLR_CH_INT_FLAG(2, PDMA_ISR_BLKD_IF_Msk);
}
else if(status & 0x8) /* CH3 */
{
if(PDMA_GET_CH_INT_STS(3) & 0x2)
temp=1;
PDMA_CLR_CH_INT_FLAG(3, PDMA_ISR_BLKD_IF_Msk);
}
else if(status & 0x10) /* CH4 */
{
if(PDMA_GET_CH_INT_STS(4) & 0x2)
PDMA_CLR_CH_INT_FLAG(4, PDMA_ISR_BLKD_IF_Msk);
}
else if(status & 0x20) /* CH5 */
{
if(PDMA_GET_CH_INT_STS(5) & 0x2)
PDMA_CLR_CH_INT_FLAG(5, PDMA_ISR_BLKD_IF_Msk);
}
else
printf("unknown interrupt !!\n");
}
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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