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大家好!<br /><br />我在layout是遇到了和楼主一样的问题,然后按照rtc的实验对综合的sdc文件进行syn_noclockbuf约束.问题就出现这个地方,综合通过,有警告,无错误.但是打开sdc文件时,出现提示<br /><br />At line 5 while processing "D:/Actelprj/c51tt/synthesis/USER_CORE8051_sdc.sdc"<br />invalid command name "create_clock"<br /><br />继续打开...<br /><br /># Top Level Design Parameters<br /><br /># Clocks<br /><br />create_clock -period 10.000000 -waveform {0.000000 5.000000} clk48m<br /><br /># False Paths Between Clocks<br /><br /><br /># False Path Constraints<br /><br /><br /># Maximum Delay Constraints<br /><br /><br /># Multicycle Constraints<br /><br /><br /># Virtual Clocks<br /># Output Load Constraints<br /># Driving Cell Constraints<br /># Wire Loads<br /># set_wire_load_mode top<br /><br /># Other Constraints<br /><br /><br /><br />这个错误请问该怎么解决呢.请大家指导一下,谢谢.
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楼主
