我用QUARTUS 8.0 进行VHDL 设计，我按照建立工程-输入路径、工程名、输入top-level design entity for this projet
可是在编译的时候总是显示：
Error: Top-level design entity "aaa" is undefined
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 169 megabytes
Error: Processing ended: Tue Oct 07 12:21:25 2008
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
为什么？请高手指点 |
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