LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY T2 IS
PORT (
amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
bdata : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END T2;
ARCHITECTURE arch OF T2 IS
begin
process(amp,bdata)
variable temp: std_logic_vector(14 downto 0);
BEGIN
temp(14 downto 0)<= amp(7 DOWNTO 0)*bdata(6 DOWNTO 0);
data<=temp(14 downto 8);
end process;
END ARCH;
要将AMP*BATAT的高7位输出给DATA，但用MUX-PLUS编译有错，不知为啥 |
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