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LIBRARY IEEE; <br />USE IEEE.STD_LOGIC_1164.ALL; <br />USE IEEE.STD_LOGIC_ARITH.ALL; <br />USE IEEE.STD_LOGIC_UNSIGNED.ALL; <br /> <br />ENTITY T2 IS <br />PORT ( <br /> amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);<br /> bdata : IN STD_LOGIC_VECTOR(6 DOWNTO 0); <br /> data : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)<br /> );<br />END T2; <br />ARCHITECTURE arch OF T2 IS <br />begin<br /> process(amp,bdata)<br /> variable temp: std_logic_vector(14 downto 0);<br /> BEGIN <br /> temp(14 downto 0)<= amp(7 DOWNTO 0)*bdata(6 DOWNTO 0); <br /> data<=temp(14 downto 8);<br /> end process;<br />END ARCH;<br />要将AMP*BATAT的高7位输出给DATA，但用MUX-PLUS编译有错，不知为啥 |
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