uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
{
return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT));
}
/**
* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode
* @param pdev : Selected device
* @retval status
*/
USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_STS status = USB_OTG_OK;
USB_OTG_FSIZ_TypeDef nptxfifosize;
USB_OTG_FSIZ_TypeDef ptxfifosize;
USB_OTG_HCCHAR_TypeDef hcchar;
USB_OTG_HCFG_TypeDef hcfg;
uint32_t num_channels = 0, i = 0;
nptxfifosize.d32 = 0;
ptxfifosize.d32 = 0;
hcfg.d32 = 0;
/* configure charge pump IO */
USB_OTG_BSP_ConfigVBUS();
/* Restart the Phy Clock */
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
/* Initialize Host Configuration Register */
USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ);
hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
hcfg.b.fslssupp = 1;
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
/* Configure data FIFO sizes */
/* Rx FIFO */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_SIZE);
/* Tx FIFO */
nptxfifosize.b.depth = TXH_NP_FIFOSIZ;
nptxfifosize.b.startaddr = RX_FIFO_SIZE;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HNPTXFSIZ, nptxfifosize.d32);
ptxfifosize.b.startaddr = RX_FIFO_SIZE + TXH_NP_FIFOSIZ;
ptxfifosize.b.depth = TXH_P_FIFOSIZ;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
/* Make sure the FIFOs are flushed. */
USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */
USB_OTG_FlushRxFifo(pdev);
/* Flush out any leftover queued requests. */
num_channels = pdev->cfg.host_channels;
for (i = 0; i < num_channels; i++)
{
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS->HCCHAR);
hcchar.b.chen = 0;
hcchar.b.chdis = 1;
hcchar.b.epdir = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS->HCCHAR, hcchar.d32);
/* Clear all pending HC Interrupts */
USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS->HCINT, 0xFFFFFFFF );
}
/* Halt all channels to put them into a known state. */
for (i = 0; i < num_channels; i++)
{
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS->HCCHAR);
hcchar.b.chen = 1;
hcchar.b.chdis = 1;
hcchar.b.epdir = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS->HCCHAR, hcchar.d32);
do
{
USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP);
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS->HCCHAR);
USB_OTG_BSP_uDelay (20);
}
while (hcchar.b.chen);
}
/* Disable HALT interrupt Masks */
for (i = 0; i < num_channels; i++)
{
USB_OTG_HCGINTMSK_TypeDef hcintmsk;
hcintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS->HCGINTMSK);
hcintmsk.b.chhltd = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS->HCGINTMSK , hcintmsk.d32);
}
USB_OTG_DriveVbus(pdev, 1);
USB_OTG_EnableHostInt(pdev);
return status;
}
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