[FPGA] ISE布线约束问题

[复制链接]
984|0
 楼主| lyy3041063 发表于 2015-10-17 09:57 | 显示全部楼层 |阅读模式
Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = NR
           IO_x_x_x_x_x_x_x
           IO_x_x_x_x_x_x
           IO_x_x_x_x_x
           IO_x_x_x_x
           IO_x_x_x
           IO_x_x
           IO_x
           IO

   This may be due to either an insufficient number of sites available on the
   device, too many prohibited sites,
   or incompatible I/O Standards locked or range constrained to I/O Banks with
   valid sites.
       This situation could possibly be resolved by one (or all) of the
   following actions:
   a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by
   using LOC or range constraints.
   b) Maximizing available I/O Banks resources for special IOBs by choosing
   lower capacity I/O Banks if possible.
   c) If applicable, decreasing the number of user prohibited sites or using a
   larger device.
我UCF里根本没有用到LVCMOS25。warnings里也没什么异常啊
您需要登录后才可以回帖 登录 | 注册

本版积分规则

1

主题

2

帖子

0

粉丝
快速回复 在线客服 返回列表 返回顶部