[技术问答] NUC505 芯片内部Flash读写问题

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 楼主| huangbbb2010 发表于 2015-12-3 17:39 | 显示全部楼层 |阅读模式
用官方提供的SPIM_DMA例程在仿真环境下跑是正常的,但烧到芯片上就跑不起来。我用的是IAR开发环境,有修改过link文件,但还是跑不起来。好像每次跑到spim_open后程序就死掉了。有谁读写过内部Flash的?有没有什么建议和方法。谢谢
wangwang2015 发表于 2015-12-3 18:06 | 显示全部楼层
我们公司有技术支持,但是要加FAE QQ:2355898184,他可以帮你解决技术上问题。
奥德赛 发表于 2015-12-3 20:19 | 显示全部楼层
是不是延时时间不够呢?
yutianxiang618 发表于 2015-12-3 22:01 | 显示全部楼层
是的,我同事也遇到这个相同的问题,仿真正常,下载就跑不动了
quray1985 发表于 2015-12-5 19:59 | 显示全部楼层
把那段代码贴出来瞧瞧
 楼主| huangbbb2010 发表于 2015-12-7 09:31 | 显示全部楼层
quray1985 发表于 2015-12-5 19:59
把那段代码贴出来瞧瞧

程序其实是新唐官方网站下载的,NUC505参考例程SPIM_DMA。
void SYS_Init(void)
{      
    /* Enable  XTAL */
    CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
   
    /* Enable IP clock */
    CLK_EnableModuleClock(UART0_MODULE);
    CLK_EnableModuleClock(SPIM_MODULE);
    //CLK->APBCLK = CLK_APBCLK_UART0CKEN_Msk;     // Enable UART0 IP clock.
    //CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;     // Enable SPIM IP clock.

    /* Select IP clock source */
    /* PCLK divider = 1 (/2) */
    CLK_SetModuleClock(PCLK_MODULE, 0, 1);
    /* UART0 clock source = XIN */
    CLK_SetModuleClock(UART0_MODULE, CLK_UART0_SRC_EXT, 0);
    //CLK->CLKDIV3 &= ~(CLK_CLKDIV3_UART0DIV_Msk | CLK_CLKDIV3_UART0SEL_Msk);
   
    /* Update System Core Clock */
    CLK_SetCoreClock(100000000);
    SystemCoreClockUpdate();
   
    /* Init I/O multi-function pins */
    /* Configure multi-function pins for UART0 RXD and TXD */
        SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB0MFP_Msk) ) | SYS_GPB_MFPL_PB0MFP_UART0_TXD;
        SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB1MFP_Msk) ) | SYS_GPB_MFPL_PB1MFP_UART0_RXD;
    /* Configure multi-function pins for SPIM, Slave I/F=GPIO. */      
}

uint32_t SPIM_Open(SPIM_T *spim, uint32_t u32SPIMode, uint32_t u32BusClock)
{
#if 0   // User program will take care.
    CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;     // Enable IP clock.
#endif
        //程序执行下面这一行就死机了
    SYS->IPRST1 |= SYS_IPRST1_SPIMRST_Msk;      // Reset IP.
    SYS->IPRST1 &= ~SYS_IPRST1_SPIMRST_Msk;
    SPIM_SetIF(spim, SPIM_CTL1_IFSEL_INTERN);   
    return SPIM_SetBusClock(spim, u32BusClock);
}

void TestDMAMode(void)
{   
    SPIM_Open(SPIM, 0, SPI_BUS_CLK);               
    DoDMASnglTest();        // 1-bit DMA Read/Write test.   
    SPIM_Close(SPIM);   
}  

int main(void)
{   
    SYS_Init();   
    UART_Open(UART0, 115200);   
    TestDMAMode();      // Test SPIM DMA mode.   
    while (1);
    //return 0;
}
huangcunxiake 发表于 2015-12-7 19:32 | 显示全部楼层
新唐科技凭借多年优异的Cortex®-M MCU经验,最新力推带有24-bit Audio Codec及高容量128KB内存新产品Cortex®-M4 NuMicro™ NUC505系列。不同于市面上昂贵的DSP芯片,NUC505系列提供了高性价比Cortex®-M4 DSP芯片之首选。NUC505系列以ARM Cortex®-M4核心,搭配DSP(数字信号处理器)与FPU(浮点运算单元),运行速度高达100 MHz,内置128 KB 内存以及2 MB SPI Flash并支持4-bit数据快速传输,可满足复杂算法的应用。 高效能之NUC505系列更结合了新唐独有的外挂储存设备保护机制(PMOC),可有效保护客户开发之程序。此外,NUC505系列具备了丰富外设,涵盖USB HS Device、USB FS Host、I²S、12-bit ADC、RTC、2组I²C、3组UART等,极适合于消费电子、iPhone周边产品、物联网、云端与音频产品等等应用需求。
huangcunxiake 发表于 2015-12-7 20:02 | 显示全部楼层
  1. /**************************************************************************//**
  2. * [url=home.php?mod=space&uid=288409]@file[/url]        spim.h
  3. * [url=home.php?mod=space&uid=895143]@version[/url]     V1.00
  4. * $Revision:   1$
  5. * $Date:       14/07/10 5:00p$
  6. * [url=home.php?mod=space&uid=247401]@brief[/url]       NUC505 series SPIM driver header file
  7. *
  8. * @note
  9. * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
  10. *****************************************************************************/
  11. #ifndef __SPIM_H__
  12. #define __SPIM_H__

  13. #ifdef __cplusplus
  14. extern "C"
  15. {
  16. #endif


  17. /** @addtogroup NUC505_Device_Driver NUC505 Device Driver
  18.   @{
  19. */

  20. /** @addtogroup NUC505_SPIM_Driver SPIM Driver
  21.   @{
  22. */

  23. /** @addtogroup NUC505_SPIM_EXPORTED_CONSTANTS SPIM Exported Constants
  24.   @{
  25. */

  26. #define SPIM_CTL0_BITMODE_STAN      (0UL << SPIM_CTL0_BITMODE_Pos)              /*!< Standard mode (SPI Interface including DO, DI, HOLD, WP). \hideinitializer */
  27. #define SPIM_CTL0_BITMODE_DUAL      (1UL << SPIM_CTL0_BITMODE_Pos)              /*!< Dual mode (SPI Interface including D0, D1, HOLD, WP). \hideinitializer */
  28. #define SPIM_CTL0_BITMODE_QUAD      (2UL << SPIM_CTL0_BITMODE_Pos)              /*!< Quad mode (SPI Interface including D0, D1, D2, D3). \hideinitializer */
  29. #define SPIM_CTL0_OPMODE_IO         (0UL << SPIM_CTL0_OPMODE_Pos)               /*!< I/O Mode. \hideinitializer */
  30. #define SPIM_CTL0_OPMODE_DMAWRITE   (1UL << SPIM_CTL0_OPMODE_Pos)               /*!< DMA Write mode. \hideinitializer */
  31. #define SPIM_CTL0_OPMODE_DMAREAD    (2UL << SPIM_CTL0_OPMODE_Pos)               /*!< DMA Read mode. \hideinitializer */
  32. #define SPIM_CTL0_OPMODE_DMM        (3UL << SPIM_CTL0_OPMODE_Pos)               /*!< Direct Memory Mapping mode. \hideinitializer */
  33. #define SPIM_CTL0_CMDCODE_PAGE_PROG                 (0x02UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Page Program command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
  34. #define SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE1      (0x32UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Quad Page Program (type 1) command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
  35. #define SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE2      (0x38UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Quad Page Program (type 2) command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
  36. #define SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE3      (0x40UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Quad Page Program (type 3) command (in \ref SPIM_CTL0_OPMODE_DMAWRITE mode). \hideinitializer */
  37. #define SPIM_CTL0_CMDCODE_READ_DATA                 (0x03UL << SPIM_CTL0_CMDCODE_Pos)   /*!< Read Data command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */
  38. #define SPIM_CTL0_CMDCODE_FAST_READ                 (0x0BUL << SPIM_CTL0_CMDCODE_Pos)   /*!< Fast Read command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */
  39. #define SPIM_CTL0_CMDCODE_FAST_READ_DUAL_OUT        (0x3BUL << SPIM_CTL0_CMDCODE_Pos)   /*!< Fast Read Dual Output command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */
  40. #define SPIM_CTL0_CMDCODE_FAST_READ_QUAD_IO         (0xEBUL << SPIM_CTL0_CMDCODE_Pos)   /*!< Fast Read Quad I/O command (in \ref SPIM_CTL0_OPMODE_DMAREAD/\ref SPIM_CTL0_OPMODE_DMM mode). \hideinitializer */

  41. #define SPIM_CTL1_IFSEL_GPIO        (0UL << SPIM_CTL1_IFSEL_Pos)                /*!< SPI Interface from GPIO. \hideinitializer */
  42. #define SPIM_CTL1_IFSEL_MCP         (1UL << SPIM_CTL1_IFSEL_Pos)                /*!< SPI Interface from MCP. \hideinitializer */
  43. #define SPIM_CTL1_IFSEL_MCP64       (2UL << SPIM_CTL1_IFSEL_Pos)                /*!< SPI Interface from MCP64. \hideinitializer */
  44. #define SPIM_CTL1_IFSEL_INTERN      SPIM_CTL1_IFSEL_MCP                         /*!< SPI Interface from internal(MCP/MCP64). \hideinitializer */
  45. #define SPIM_CTL1_IFSEL_EXTERN      SPIM_CTL1_IFSEL_GPIO                        /*!< SPI Interface from external(GPIO). \hideinitializer */

  46. /* SPIM Interrupt Mask */
  47. #define SPIM_INT_MASK                   (0x001)                                 /*!< Interrupt mask. \hideinitializer */


  48. /*@}*/ /* end of group NUC505_SPIM_EXPORTED_CONSTANTS */

  49. /** @addtogroup NUC505_SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions
  50.   @{
  51. */

  52. /**
  53.   * @brief                  Enable I/O mode.
  54.   * @param[in]  spim        Base address of SPIM module.
  55.   * @param[in]  u32BitMode  Bit mode. Valid values include:
  56.   *                         - \ref SPIM_CTL0_BITMODE_STAN
  57.   *                         - \ref SPIM_CTL0_BITMODE_DUAL
  58.   *                         - \ref SPIM_CTL0_BITMODE_QUAD
  59.   * @param[in]  u32QDIODir  I/O direction for Quad/Dual mode. Valid values can be 0 (for input) or 1 (for output).
  60.   * [url=home.php?mod=space&uid=266161]@return[/url]                 None.
  61.   * \hideinitializer
  62.   */
  63. #define SPIM_ENABLE_IO_MODE(spim, u32BitMode, u32QDIODir) \
  64.     do {    \
  65.         (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_BITMODE_Msk))) | (u32BitMode);   \
  66.         (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_QDIODIR_Msk))) | ((u32QDIODir) << SPIM_CTL0_QDIODIR_Pos);   \
  67.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | SPIM_CTL0_OPMODE_IO;    \
  68.     } while (0)

  69. /**
  70.   * @brief                  Set bit mode for I/O mode.
  71.   * @param[in]  spim        Base address of SPIM module.
  72.   * @param[in]  u32BitMode  Bit mode. Valid values include:
  73.   *                         - \ref SPIM_CTL0_BITMODE_STAN
  74.   *                         - \ref SPIM_CTL0_BITMODE_DUAL
  75.   *                         - \ref SPIM_CTL0_BITMODE_QUAD
  76.   * @return                 None.
  77.   * \hideinitializer
  78.   */
  79. #define SPIM_SET_BIT_MODE(spim, u32BitMode)  \
  80.     do {    \
  81.         (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_BITMODE_Msk))) | (u32BitMode);    \
  82.     } while (0)

  83. /**
  84.   * @brief                  Set direction for Quad/Dual I/O mode.
  85.   * @param[in]  spim        Base address of SPIM module.
  86.   * @param[in]  u32Dir      Direction. Valid values can be 0 (for input) and 1 (for output).
  87.   * @return                 None.
  88.   * \hideinitializer
  89.   */
  90. #define SPIM_SET_QDIODIR(spim, u32Dir)  \
  91.     do {    \
  92.         (spim)->CTL0 = ((spim)->CTL0 & (~(SPIM_CTL0_QDIODIR_Msk))) | (((u32Dir) ? 1 : 0) << SPIM_CTL0_QDIODIR_Pos);    \
  93.     } while (0)


  94. /**
  95.   * @brief                  Enable DMA mode.
  96.   * @param[in]  spim        Base address of SPIM module.
  97.   * @param[in]  isWrite     0 for DMA Read mode; 1 for DMA Write mode.
  98.   * @param[in]  u32CmdCode  Command code.
  99.   * - Valid values for DMA Write mode include:
  100.   *     - \ref SPIM_CTL0_CMDCODE_PAGE_PROG
  101.   *     - \ref SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE1
  102.   *     - \ref SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE2
  103.   *     - \ref SPIM_CTL0_CMDCODE_QUAD_PAGE_PROG_TYPE3
  104.   * - Valid values for DMA Read mode include:
  105.   *     - \ref SPIM_CTL0_CMDCODE_READ_DATA
  106.   *     - \ref SPIM_CTL0_CMDCODE_FAST_READ
  107.   *     - \ref SPIM_CTL0_CMDCODE_FAST_READ_DUAL_OUT
  108.   *     - \ref SPIM_CTL0_CMDCODE_FAST_READ_QUAD_IO
  109.   * @param[in]  is4ByteAddr 4-byte address or not.
  110.   * @return                 None.
  111.   * \hideinitializer
  112.   */
  113. #define SPIM_ENABLE_DMA_MODE(spim, isWrite, u32CmdCode, is4ByteAddr) \
  114.     do {    \
  115.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (u32CmdCode);  \
  116.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | ((is4ByteAddr) << SPIM_CTL0_B4ADDREN_Pos);    \
  117.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (isWrite ? SPIM_CTL0_OPMODE_DMAWRITE : SPIM_CTL0_OPMODE_DMAREAD);    \
  118.     } while (0)

  119. /**
  120.   * @brief                  Enable Direct Memory Mapping (DMM) mode.
  121.   * @param[in]  spim        Base address of SPIM module.
  122.   * @param[in]  u32ReadCmdCode  Read command code. Valid values include:
  123.   *                         - \ref SPIM_CTL0_CMDCODE_READ_DATA
  124.   *                         - \ref SPIM_CTL0_CMDCODE_FAST_READ
  125.   *                         - \ref SPIM_CTL0_CMDCODE_FAST_READ_DUAL_OUT
  126.   *                         - \ref SPIM_CTL0_CMDCODE_FAST_READ_QUAD_IO
  127.   * @param[in]  is4ByteAddr 4-byte address or not.
  128.   * @return                 None.
  129.   * \hideinitializer
  130.   */
  131. #define SPIM_ENABLE_DMM_MODE(spim, u32ReadCmdCode, is4ByteAddr) \
  132.     do {    \
  133.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (u32ReadCmdCode);  \
  134.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | ((is4ByteAddr) << SPIM_CTL0_B4ADDREN_Pos);    \
  135.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (SPIM_CTL0_OPMODE_DMM);    \
  136.     } while (0)

  137. /**
  138.   * @brief                      Set the length of suspend interval.
  139.   * @param[in]  spim            Base address of SPIM module.
  140.   * @param[in]  u32SuspCycle    Decides the length of suspend interval which ranges between 0 and 15.
  141.   * @return                     None.
  142.   * \hideinitializer
  143.   */
  144. #define SPIM_SET_SUSPEND_CYCLE(spim, u32SuspCycle) \
  145.     do {    \
  146.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_SLEEP_Msk)) | ((u32SuspCycle) << SPIM_CTL0_SLEEP_Pos);    \
  147.     } while (0)

  148. /**
  149.   * @brief                      Set the number of successive transmit/receive transactions in one transfer.
  150.   * @param[in]  spim            Base address of SPIM module.
  151.   * @param[in]  u32BurstNum     Decides the transmit/receive number in one transfer which ranges between 1 and 4.
  152.   * @return                     None.
  153.   * \hideinitializer
  154.   */
  155. #define SPIM_SET_BURST_NUM(spim, u32BurstNum) \
  156.     do {    \
  157.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((u32BurstNum) - 1) << SPIM_CTL0_BURSTNUM_Pos);  \
  158.     } while (0)

  159. /**
  160.   * @brief                  Set the data width of a transmit/receive transaction.
  161.   * @param[in]  spim        Base address of SPIM module.
  162.   * @param[in]  u32Width    Data width which ranges between 1 and 32.
  163.   * @return                 None.
  164.   * \hideinitializer
  165.   */
  166. #define SPIM_SET_DATA_WIDTH(spim, u32Width)   \
  167.     do {    \
  168.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((u32Width) - 1) << SPIM_CTL0_DWIDTH_Pos);  \
  169.     } while (0)

  170. /**
  171.   * @brief              Disable cipher.
  172.   * [url=home.php?mod=space&uid=536309]@NOTE[/url]               Cipher can only be disabled and cannot be enabled.
  173.   * @param[in]  spim    Base address of SPIM module.
  174.   * @return             None.
  175.   * \hideinitializer
  176.   */
  177. #define SPIM_DISABLE_CIPHER(spim) \
  178.     do {    \
  179.         (spim)->CTL0 = ((spim)->CTL0 & (~SPIM_CTL0_CipherDis_Msk)) | ((! (0)) << SPIM_CTL0_CipherDis_Pos); \
  180.     } while (0)

  181. /**
  182.   * @brief              Set slave select pin to high state.
  183.   * @param[in]  spim    Base address of SPIM module.
  184.   * @return             None.
  185.   * \hideinitializer
  186.   */
  187. #define SPIM_SET_SS_HIGH(spim) \
  188.     do {    \
  189.         ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((0) << SPIM_CTL1_SSACTPOL_Pos));   \
  190.         ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (0)) << SPIM_CTL1_SS_Pos)); \
  191.     } while (0)

  192. /**
  193.   * @brief              Set slave select pin to low state.
  194.   * @param[in]  spim    Base address of SPIM module.
  195.   * @return             None.
  196.   * \hideinitializer
  197.   */
  198. #define SPIM_SET_SS_LOW(spim) \
  199.     do {    \
  200.         ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((0) << SPIM_CTL1_SSACTPOL_Pos));   \
  201.         ((spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (1)) << SPIM_CTL1_SS_Pos)); \
  202.     } while (0)

  203. /**
  204.   * @brief              Check if SPIM module is busy.
  205.   * @param[in]  spim    Base address of SPIM module.
  206.   * @retval 0           Not busy.
  207.   * @retval 1           Busy.
  208.   * \hideinitializer
  209.   */
  210. #define SPIM_IS_BUSY(spim) \
  211.     (!!((spim)->CTL1 & SPIM_CTL1_SPIMEN_Msk))

  212. /**
  213.   * @brief              Trigger SPI transfer.
  214.   * @param[in]  spim    Base address of SPIM module.
  215.   * @return             None.
  216.   * \hideinitializer
  217.   */
  218. #define SPIM_TRIGGER(spim)  \
  219.     do {    \
  220.         (spim)->CTL1 = ((spim)->CTL1 & (~SPIM_CTL1_SPIMEN_Msk)) | SPIM_CTL1_SPIMEN_Msk;   \
  221.     } while (0)

  222. /**
  223.   * @brief                  Write datum to TX0 register.
  224.   * @param[in]  spim        Base address of SPIM module.
  225.   * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  226.   * @return                 None.
  227.   * \hideinitializer
  228.   */
  229. #define SPIM_WRITE_TX0(spim, u32TxData)   \
  230.     do {    \
  231.         (spim)->TX0 = u32TxData;  \
  232.     } while (0)

  233. /**
  234.   * @brief                  Write datum to TX1 register.
  235.   * @param[in]  spim        Base address of SPIM module.
  236.   * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  237.   * @return                 None.
  238.   * \hideinitializer
  239.   */
  240. #define SPIM_WRITE_TX1(spim, u32TxData)   \
  241.     do {    \
  242.         (spim)->TX1 = u32TxData;  \
  243.     } while (0)

  244. /**
  245.   * @brief                  Write datum to TX2 register.
  246.   * @param[in]  spim        Base address of SPIM module.
  247.   * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  248.   * @return                 None.
  249.   * \hideinitializer
  250.   */
  251. #define SPIM_WRITE_TX2(spim, u32TxData)   \
  252.     do {    \
  253.         (spim)->TX2 = u32TxData;  \
  254.     } while (0)

  255. /**
  256.   * @brief                  Write datum to TX3 register.
  257.   * @param[in]  spim        Base address of SPIM module.
  258.   * @param[in]  u32TxData   Data which user attempts to transfer through SPI bus.
  259.   * @return                 None.
  260.   * \hideinitializer
  261.   */
  262. #define SPIM_WRITE_TX3(spim, u32TxData)   \
  263.     do {    \
  264.         (spim)->TX3 = u32TxData;  \
  265.     } while (0)

  266. /**
  267.   * @brief                  Get the datum read from RX0 register.
  268.   * @param[in]  spim        Base address of SPIM module.
  269.   * @return                 Datum read from RX0 register.
  270.   * \hideinitializer
  271.   */
  272. #define SPIM_READ_RX0(spim)     (spim)->RX0

  273. /**
  274.   * @brief                  Get the datum read from RX1 register.
  275.   * @param[in]  spim        Base address of SPIM module.
  276.   * @return                 Datum read from RX1 register.
  277.   * \hideinitializer
  278.   */
  279. #define SPIM_READ_RX1(spim)     (spim)->RX1

  280. /**
  281.   * @brief                  Get the datum read from RX2 register.
  282.   * @param[in]  spim        Base address of SPIM module.
  283.   * @return                 Datum read from RX2 register.
  284.   * \hideinitializer
  285.   */
  286. #define SPIM_READ_RX2(spim)     (spim)->RX2

  287. /**
  288.   * @brief                  Get the datum read from RX3 register.
  289.   * @param[in]  spim        Base address of SPIM module.
  290.   * @return                 Datum read from RX3 register.
  291.   * \hideinitializer
  292.   */
  293. #define SPIM_READ_RX3(spim)     (spim)->RX3

  294. uint32_t SPIM_Open(SPIM_T *spim, uint32_t u32SPIMode, uint32_t u32BusClock);
  295. void SPIM_Close(SPIM_T *spim);
  296. uint32_t SPIM_SetBusClock(SPIM_T *spim, uint32_t u32BusClock);
  297. uint32_t SPIM_GetBusClock(SPIM_T *spim);
  298. void SPIM_EnableInt(SPIM_T *spim, uint32_t u32Mask);
  299. void SPIM_DisableInt(SPIM_T *spim, uint32_t u32Mask);
  300. uint32_t SPIM_GetIntFlag(SPIM_T *spim, uint32_t u32Mask);
  301. void SPIM_ClearIntFlag(SPIM_T *spim, uint32_t u32Mask);
  302. void SPIM_SetIF(SPIM_T *spim, uint32_t u32IFSel);

  303. void SPIM_DMAWritePage(SPIM_T *spim, uint32_t u32FlashAddr, uint32_t u32Len, uint8_t *pu8TxBuf);
  304. void SPIM_DMAReadFlash(SPIM_T *spim, uint32_t u32FlashAddr, uint32_t u32Len, uint8_t *pu8RxBuf);

  305. /*@}*/ /* end of group NUC505_SPIM_EXPORTED_FUNCTIONS */

  306. /*@}*/ /* end of group NUC505_SPIM_Driver */

  307. /*@}*/ /* end of group NUC505_Device_Driver */

  308. #ifdef __cplusplus
  309. }
  310. #endif

  311. #endif //__SPIM_H__

  312. /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/


huangcunxiake 发表于 2015-12-7 20:02 | 显示全部楼层
QQ截图20151204091454.png
不知道这是个什么图,有人知道没
史迪威将军 发表于 2015-12-7 20:56 | 显示全部楼层
有可能是复位电路有问题,仿真的时候是软复位吧
C洛达尔多 发表于 2015-12-9 20:34 | 显示全部楼层
感觉是硬件的复位电路没处理好
zhuotuzi 发表于 2015-12-9 20:51 | 显示全部楼层
带有24-bit Audio Codec及高容量128KB内存新产品Cortex®-M4 NuMicro™ NUC505系列。不同于市面上昂贵的DSP芯片,NUC505系列提供了高性价比Cortex®-M4 DSP芯片之首选。
Beckham_Owen 发表于 2015-12-12 21:37 | 显示全部楼层
楼主问题解决了吗,我这里也有人遇到了同样的问题
捉虫天师 发表于 2016-6-19 22:04 | 显示全部楼层
啥问题,好多人不会啊。
捉虫天师 发表于 2016-6-19 22:15 | 显示全部楼层
  1. /**************************************************************************//**
  2. * [url=home.php?mod=space&uid=288409]@file[/url]     main.c
  3. * [url=home.php?mod=space&uid=895143]@version[/url]  V2.0
  4. * $Revision: 11 $
  5. * $Date: 15/03/04 9:47a $
  6. * [url=home.php?mod=space&uid=247401]@brief[/url]    Access the SPI Flash through a SPI interface.
  7. *
  8. * @note
  9. * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
  10. *
  11. ******************************************************************************/
  12. #include <stdio.h>
  13. #include "NUC505Series.h"

  14. #define TEST_NUMBER 1   /* page numbers */
  15. #define TEST_LENGTH 256 /* length */

  16. #define SPI_FLASH_PORT  SPI0

  17. uint8_t SrcArray[TEST_LENGTH];
  18. uint8_t DestArray[TEST_LENGTH];

  19. /* Function prototype declaration */
  20. void SYS_Init(void);
  21. void UART0_Init(void);
  22. void SPI0_Init(void);

  23. uint16_t SpiFlash_ReadMidDid(void)
  24. {
  25.     uint8_t u8RxData[6], u8IDCnt = 0;

  26.     // /CS: active
  27.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  28.     // send Command: 0x90, Read Manufacturer/Device ID
  29.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x90);

  30.     // send 24-bit '0', dummy
  31.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
  32.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
  33.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);

  34.     // receive 16-bit
  35.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
  36.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);

  37.     // wait tx finish
  38.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  39.     // /CS: de-active
  40.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);

  41.     while(!SPI_GET_RX_FIFO_EMPTY_FLAG(SPI_FLASH_PORT))
  42.         u8RxData[u8IDCnt ++] = SPI_READ_RX(SPI_FLASH_PORT);

  43.     return ( (u8RxData[4]<<8) | u8RxData[5] );
  44. }

  45. void SpiFlash_ChipErase(void)
  46. {
  47.     // /CS: active
  48.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  49.     // send Command: 0x06, Write enable
  50.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);

  51.     // wait tx finish
  52.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  53.     // /CS: de-active
  54.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);

  55.     //////////////////////////////////////////

  56.     // /CS: active
  57.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  58.     // send Command: 0xC7, Chip Erase
  59.     SPI_WRITE_TX(SPI_FLASH_PORT, 0xC7);

  60.     // wait tx finish
  61.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  62.     // /CS: de-active
  63.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);

  64.     SPI_ClearRxFIFO(SPI0);
  65. }

  66. uint8_t SpiFlash_ReadStatusReg(void)
  67. {
  68.     // /CS: active
  69.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  70.     // send Command: 0x05, Read status register
  71.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x05);

  72.     // read status
  73.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);

  74.     // wait tx finish
  75.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  76.     // /CS: de-active
  77.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);

  78.     // skip first rx data
  79.     SPI_READ_RX(SPI_FLASH_PORT);

  80.     return (SPI_READ_RX(SPI_FLASH_PORT) & 0xff);
  81. }

  82. void SpiFlash_WriteStatusReg(uint8_t u8Value)
  83. {
  84.     // /CS: active
  85.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  86.     // send Command: 0x06, Write enable
  87.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);

  88.     // wait tx finish
  89.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  90.     // /CS: de-active
  91.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);

  92.     ///////////////////////////////////////

  93.     // /CS: active
  94.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  95.     // send Command: 0x01, Write status register
  96.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x01);

  97.     // write status
  98.     SPI_WRITE_TX(SPI_FLASH_PORT, u8Value);

  99.     // wait tx finish
  100.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  101.     // /CS: de-active
  102.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);
  103. }

  104. void SpiFlash_WaitReady(void)
  105. {
  106.     uint8_t ReturnValue;

  107.     do {
  108.         ReturnValue = SpiFlash_ReadStatusReg();
  109.         ReturnValue = ReturnValue & 1;
  110.     } while(ReturnValue!=0); // check the BUSY bit
  111. }

  112. void SpiFlash_NormalPageProgram(uint32_t StartAddress, uint8_t *u8DataBuffer)
  113. {
  114.     uint32_t i = 0;

  115.     // /CS: active
  116.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  117.     // send Command: 0x06, Write enable
  118.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x06);

  119.     // wait tx finish
  120.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  121.     // /CS: de-active
  122.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);


  123.     // /CS: active
  124.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  125.     // send Command: 0x02, Page program
  126.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x02);

  127.     // send 24-bit start address
  128.     SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
  129.     SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8)  & 0xFF);
  130.     SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress       & 0xFF);

  131.     // write data
  132.     while(1) {
  133.         if(!SPI_GET_TX_FIFO_FULL_FLAG(SPI_FLASH_PORT)) {
  134.             SPI_WRITE_TX(SPI_FLASH_PORT, u8DataBuffer[i++]);
  135.             if(i >= 255) break;
  136.         }
  137.     }

  138.     // wait tx finish
  139.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  140.     // /CS: de-active
  141.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);

  142.     SPI_ClearRxFIFO(SPI_FLASH_PORT);
  143. }

  144. void SpiFlash_NormalRead(uint32_t StartAddress, uint8_t *u8DataBuffer)
  145. {
  146.     uint32_t i;

  147.     // /CS: active
  148.     SPI_SET_SS_LOW(SPI_FLASH_PORT);

  149.     // send Command: 0x03, Read data
  150.     SPI_WRITE_TX(SPI_FLASH_PORT, 0x03);

  151.     // send 24-bit start address
  152.     SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>16) & 0xFF);
  153.     SPI_WRITE_TX(SPI_FLASH_PORT, (StartAddress>>8)  & 0xFF);
  154.     SPI_WRITE_TX(SPI_FLASH_PORT, StartAddress       & 0xFF);

  155.     while(SPI_IS_BUSY(SPI_FLASH_PORT));
  156.     // clear RX buffer
  157.     SPI_ClearRxFIFO(SPI_FLASH_PORT);

  158.     // read data
  159.     for(i=0; i<256; i++) {
  160.         SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
  161.         while(SPI_IS_BUSY(SPI_FLASH_PORT));
  162.         u8DataBuffer[i] = SPI_READ_RX(SPI_FLASH_PORT);
  163.     }

  164.     // wait tx finish
  165.     while(SPI_IS_BUSY(SPI_FLASH_PORT));

  166.     // /CS: de-active
  167.     SPI_SET_SS_HIGH(SPI_FLASH_PORT);
  168. }

  169. /* Main */
  170. int main(void)
  171. {
  172.     uint32_t u32ByteCount, u32FlashAddress, u32PageNumber;
  173.     uint32_t nError = 0;
  174.     uint16_t u16ID;

  175.     /* Init System, IP clock and multi-function I/O */
  176.     SYS_Init();

  177.     /* Init UART0 to 115200-8n1 for print message */
  178.     UART0_Init();

  179.                 /* Init SPI0, IP clock and multi-function I/O */
  180.                 SPI0_Init();
  181.                
  182.     /* Configure SPI_FLASH_PORT as a master, MSB first, 8-bit transaction, SPI Mode-0 timing, clock is 2MHz */
  183.     SPI_Open(SPI_FLASH_PORT, SPI_MASTER, SPI_MODE_0, 8, 2000000);

  184.     /* Enable the automatic hardware slave select function. Select the SS0 pin and configure as low-active. */
  185.     SPI_EnableAutoSS(SPI_FLASH_PORT, SPI_SS, SPI_SS_ACTIVE_LOW);
  186.     SPI_ENABLE(SPI_FLASH_PORT);

  187.     printf("\n+------------------------------------------------------------------------+\n");
  188.     printf("|            NUC505        SPI Sample with SPI Flash                     |\n");
  189.     printf("+------------------------------------------------------------------------+\n");

  190.     /* Wait ready */
  191.     SpiFlash_WaitReady();

  192. ///    if((u16ID = SpiFlash_ReadMidDid()) != 0x1C14) {
  193.                 if((u16ID = SpiFlash_ReadMidDid()) != 0xEF14) {
  194.         printf("Wrong ID, 0x%x\n", u16ID);
  195.         return -1;
  196.     } else
  197.         printf("Flash found: Winbond 25Q16OVSEG ...\n");

  198.     printf("Erase chip ...");

  199.     /* Erase SPI flash */
  200.     SpiFlash_ChipErase();

  201.     /* Wait ready */
  202.     SpiFlash_WaitReady();

  203.     printf("[OK]\n");

  204.     /* init source data buffer */
  205.     for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
  206.         SrcArray[u32ByteCount] = u32ByteCount;
  207.     }

  208.     printf("Start to normal write data to Flash ...");
  209.     /* Program SPI flash */
  210.     u32FlashAddress = 0;
  211.     for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++) {
  212.         /* page program */
  213.         SpiFlash_NormalPageProgram(u32FlashAddress, SrcArray);
  214.         SpiFlash_WaitReady();
  215.         u32FlashAddress += 0x100;
  216.     }

  217.     printf("[OK]\n");

  218.     /* clear destination data buffer */
  219.     for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
  220.         DestArray[u32ByteCount] = 0;
  221.     }

  222.     printf("Normal Read & Compare ...");

  223.     /* Read SPI flash */
  224.     u32FlashAddress = 0;
  225.     for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++) {
  226.         /* page read */
  227.         SpiFlash_NormalRead(u32FlashAddress, DestArray);
  228.         u32FlashAddress += 0x100;

  229.         for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
  230.             if(DestArray[u32ByteCount] != SrcArray[u32ByteCount])
  231.                 nError ++;
  232.         }
  233.     }

  234.     if(nError == 0)
  235.         printf("[OK]\n");
  236.     else
  237.         printf("[FAIL]\n");

  238.     while(1);
  239. }

  240. void SYS_Init(void)
  241. {

  242. /*---------------------------------------------------------------------------------------------------------*/
  243. /* Init System Clock                                                                                       */
  244. /*---------------------------------------------------------------------------------------------------------*/
  245.     /* Unlock protected registers */
  246.     //SYS_UnlockReg();
  247.      
  248.     /* Enable  XTAL */
  249.     CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;

  250.     CLK_SetCoreClock(FREQ_96MHZ);
  251.    
  252.                 /* PCLK divider */
  253.                 CLK_SetModuleClock(PCLK_MODULE, NULL, 1);
  254.                
  255.     /* Lock protected registers */
  256.     //SYS_LockReg();
  257.         
  258. }

  259. void UART0_Init(void)
  260. {
  261.                 /* Enable UART0 Module clock */
  262.     CLK_EnableModuleClock(UART0_MODULE);
  263.                 /* UART0 module clock from EXT */
  264.                 CLK_SetModuleClock(UART0_MODULE, CLK_UART0_SRC_EXT, 0);
  265.     /* Reset IP */
  266.     SYS_ResetModule(UART0_RST);   
  267.     /* Configure UART0 and set UART0 Baud-rate */
  268.                 UART_Open(UART0, 115200);
  269.                 /*---------------------------------------------------------------------------------------------------------*/
  270.     /* Init I/O Multi-function                                                                                 */
  271.     /*---------------------------------------------------------------------------------------------------------*/
  272.     /* Configure multi-function pins for UART0 RXD and TXD */
  273.                 SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB0MFP_Msk) ) | SYS_GPB_MFPL_PB0MFP_UART0_TXD;       
  274.                 SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB1MFP_Msk) ) | SYS_GPB_MFPL_PB1MFP_UART0_RXD;       
  275.        
  276. }

  277. void SPI0_Init(void)
  278. {
  279.                 /* Enable SPI0 Module clock */
  280.     CLK_EnableModuleClock(SPI0_MODULE);
  281.                 /* SPI0 module clock from EXT */
  282.                 CLK_SetModuleClock(SPI0_MODULE, CLK_SPI0_SRC_PLL, 0);
  283.     /* Reset IP */
  284.     SYS_ResetModule(SPI0_RST);   
  285.     /*---------------------------------------------------------------------------------------------------------*/
  286.     /* Init I/O Multi-function                                                                                 */
  287.     /*---------------------------------------------------------------------------------------------------------*/
  288.     /* Configure multi-function pins for SPI0 */
  289.                 SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB2MFP_Msk) ) | SYS_GPB_MFPL_PB2MFP_SPI0_SS;       
  290.                 SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB3MFP_Msk) ) | SYS_GPB_MFPL_PB3MFP_SPI0_CLK;       
  291.                 SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB4MFP_Msk) ) | SYS_GPB_MFPL_PB4MFP_SPI0_MOSI;       
  292.                 SYS->GPB_MFPL  = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB5MFP_Msk) ) | SYS_GPB_MFPL_PB5MFP_SPI0_MISO;       
  293.        
  294. }

  295. /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/

这个是吧
Qwo 发表于 2018-6-1 19:22 | 显示全部楼层
我也遇到这个问题了,楼主解决了吗?
hijxyz 发表于 2019-5-9 13:39 | 显示全部楼层
我也遇到这个问题了,怎么就解决呢
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