飞思卡尔K02时钟配置问题

只看该作者 · 2015-12-4 09:19

我想用外部8M的时钟配置成72M的系统时钟，下面是我配置的代码，大神给我解释一下为什么不行？我用的是KEIL5
代码如下：
SIM->CLKDIV1 = (uint32_t)0xFFFFFFFFu; //ÅäÖÃÏµÍ³Ô¤·ÖÆµÆ÷ ÏÈÉèÖÃÎª¶¼Îª×îµÍ·ÖÆµ
//×ªµ½ FBE Ä£Ê½
SIM_SCGC5  |=SIM_SCGC5_PORTA_MASK;
/* MCG_C2: LOCRE0=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
            MCG_C2_LOCRE0_MASK |
            MCG_C2_RANGE(0x01) |
            MCG_C2_HGO_MASK |
            MCG_C2_LP_MASK |
            MCG_C2_IRCS_MASK
         )) | (uint8_t)(
            MCG_C2_RANGE(0x01) |
MCG_C2_HGO_MASK |
MCG_C2_EREFS_MASK
         ));
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG->C1 |=MCG_C1_CLKS(0x02) |
            MCG_C1_FRDIV(0x04)|
MCG_C1_IREFS_MASK; //Íâ²¿Ê±ÖÓÑ¡Ôñ

/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
// OSC_CR = OSC_CR_ERCLKEN_MASK;
OSC->CR = (uint8_t)0x00u;
/* MCG_C7: OSCSEL=0 */
SystemCoreClock = 8000000;
MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL(0x03));
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u);
//  while((MCG->S & MCG_S_IRCST_MASK) != 0u);
while((MCG->S & 0x0Cu) != 0x08u);

只看该作者 · 2015-12-4 11:32

建议楼主使用我们提供的时钟模式建立函数，里面有提供5种模式供你选择：
/* Predefined clock setups
0 ... Default  part configuration
      Multipurpose Clock Generator (MCG) in FEI mode.
      Reference clock source for MCG module: Slow internal reference clock
      Core clock = 20.97152MHz
      Bus clock  = 20.97152MHz
1 ... Maximum achievable clock frequency configuration
      Multipurpose Clock Generator (MCG) in FEE mode.
      Reference clock source for MCG module: System oscillator 0 reference clock
      Core clock = 80MHz
      Bus clock  = 40MHz
2 ... Internally clocked, ready for Very Low Power Run mode.
      Multipurpose Clock Generator (MCG) in BLPI mode.
      Reference clock source for MCG module: Fast internal reference clock
      Core clock = 4MHz
      Bus clock  = 4MHz
3 ... Externally clocked, ready for Very Low Power Run mode.
      Multipurpose Clock Generator (MCG) in BLPE mode.
      Reference clock source for MCG module: System oscillator 0 reference clock
      Core clock = 4MHz
      Bus clock  = 4MHz
4 ... Maximum achievable clock frequency configuration in RUN mode
      Multipurpose Clock Generator (MCG) in FEE mode.
      Reference clock source for MCG module: System oscillator 0 reference clock
      Core clock = 60MHz
      Bus clock  = 30MHz
*/

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