我写了两个，一个是全加器，一个是其TESTBENCH
前者编译通过，后者死活不行。高手帮我看看，指点指点，
万分感谢！
--Full_Adder2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity full_adder2 is
port( x, y, cin : in std_logic ;
sum, cout : out std_logic ) ;
end full_adder2 ;
architecture b_adder of full_adder2 is
signal s : std_logic;
begin
s <= x xor cin;
sum <= s xor cin;
cout <= ( s and cin ) or ( x and y ) ;
end b_adder ;
=================================================
-- Full_Adder2_TestBench.vhd
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.numeric_std.all ;
entity e_adder is
end e_adder ;
architecture e_adder of e_adder is
component full_adder2
port( x , y , cin : in std_logic ;
sum, cout : out std_logic ) ;
end component ;
for all:full_adder2 use entity work.full_adder2(b_adder);
begin
x <= '0', '1' after 150ns,
'0' after 200ns,
'1' after 250ns,
'0' after 400ns ;
y <= '0', '1'after 100ns,
'0' after 150ns,
'1' after 200ns,
'0' after 300ns,
'1' after 350ns,
'0' after 400ns ;
cin <= '0', '1' after 50ns,
'0' after 100ns,
'1' after 200ns,
'0' after 250ns,
'1' after 300ns,
'0' after 400ns ;
end e_adder ;
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