VHDL编译报错，请高手指点错误。

只看该作者 · 2007-7-12 09:03

8位比较器，大于DCH时，输出＝1，否则＝0，VHDL程序如下：
LIBRARY  IEEE ;
USE  IEEE.STD_LOGIC_1164.ALL ;
ENTITY  comparator_bc  IS  --  表示8位数值比较器>=DCH,
PORT (  dataA  :  IN  STD_LOGIC_VECTOR ( 7 DOWNTO  0 ) ;
        rfmute :  IN STD_LOGIC;
        greater_bc  :  OUT  STD_LOGIC ;  --  A大于DCH输出信号
END  ENTITY  comparator_bc ;

ARCHITECTURE  behavioral  OF  comparator_bc IS
SIGNAL  dataB : IN  STD_LOGIC_VECTOR ( 7 DOWNTO  0 ) ;

BEGIN
inst_comparator : PROCESS ( rfmute,dataA, dataB )
BEGIN
    dataB <= "11011100";   --dataB=DCH
    IF  ( rfmute='1'  )  THEN
            FOR  i  IN  7  DOWNTO  0  LOOP
            IF  ( dataA ( i ) = '1'  AND  dataB ( i ) = '0' )  THEN
               greater_bc  <=   '1' ;
            EXIT ;   --  已经判断出dataA> dataB,则跳出循环

            ELSE
               greater_bc  <=   '0' ;
            END LOOP;
    ELSE
    greater_bc  <=   '0' ;
    END  IF ;
END  PROCESS  inst_comparator ;
END  ARCHITECTURE  behavioral ;

编译总是报错
Error (10500): VHDL syntax error at comparator_bc.vhd(7) near text "END";  expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at comparator_bc.vhd(12) near text "BEGIN";  expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at comparator_bc.vhd(13) near text ")";  expecting ":", or ","

请高手指点。谢谢