本人前两天用Verilog在Quartus II下写了个计数器，用来输出多个脉冲的。clk为100MHz时钟，想实现当U2输入一个几十ns的脉冲信号后，OP输出在一定的时间间隔后输出几个几十ns的脉冲。仿真的结果是OP出了nnn个脉冲，并不是我想要的结果。希望不幸看到这帖子的各位的江湖救急，能指点一二，感谢：）
module epm7000(OP, U2,clk);
input U2,clk; //U2为输入脉冲，clk为100MHz时钟
output OP; //脉冲输出
reg OP;
reg start,stop;
reg [15:0]out;
always @(posedge U2 or negedge stop or posedge clk)//设置启停
begin
if(U2)
begin
start <= 0;
end
if(stop == 0)
begin
start <= 1;
end
end
always @(posedge clk or negedge start)//计数出脉冲
begin
if(start == 0)
begin
out <= out + 1;
case(out)
16'H0042: OP <= 1; //1脉冲
16'H004C: OP <= 0;
16'H014D: OP <= 1; //2脉冲
16'H0157: OP <= 0;
16'H029B: OP <= 1; //3
16'H02A5: OP <= 0;
16'H0536: OP <= 1; //4
16'H0540: OP <= 0;
16'H07D1: OP <= 1; //5
16'H07DB: OP <= 0;
16'H07F2: OP <= 1; //6
16'H07FC: OP <= 0;
16'H0D08: OP <= 1; //7
16'H0D12: OP <= 0;
16'H1A11: OP <= 1; //8
16'H1A1B: OP <= 0;
16'H2EE8: OP <= 1; //9
16'H2EF2: OP <= 0;
16'H4000: stop <= 0; //停止
//default:;
endcase
end
else
begin //复位
OP <= 0;
out <= 0;
stop <=1;
end
end
endmodule
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