library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity haohao is
port(clkk:in std_logic;
ret:in std_logic;
clk1hz:out std_logic);
end haohao;
architecture behav of haohao is
signal div2clk : integer range 7 downto 0;
signal kk1: std_logic;
begin
process(clkk,ret)
begin
if ret='1' then kk1<='0';
elsif div2clk=5 then kk1<=not kk1; div2clk<=0;
elsif clkk'event and clkk='1' then div2clk<=div2clk+1;
end if;
end process;
clk1hz<=kk1;
end behav; |
楼主
标题置顶
标题高亮
