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我是一个新手，刚编译一个乘法器程序，可总是有问题，不知怎么改，vhdl程序如下:<br />library IEEE;<br /> use IEEE.Std_logic_1164.all;<br /> <br /> ENTITY booth_multiplier IS<br /> GENERIC(k POSITIVE := 7);<br /> PORT(multiplicand, multiplier : IN BIT_VECTOR(k DOWNTO 0);<br /> clock : IN BIT; product : INOUT BIT_VECTOR((2*k + 1) DOWNTO 0));<br /> END booth_multiplier;<br /> <br /> ARCHITECTURE structural OF booth_multiplier IS<br /> <br /> SIGNAL mdreg, adderout, carries, augend, tcbuffout : BIT_VECTOR(k DOWNTO 0);<br /> SIGNAL mrreg : BIT_VECTOR((k + 1) DOWNTO 0);<br /> SIGNAL adder_ovfl : BIT;<br /> SIGNAL comp ,clr_mr ,load_mr ,shift_mr ,clr_md ,load_md ,clr_pp ,load_pp ,shift_pp : BIT;<br /> SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1);<br /> <br /> BEGIN<br /> <br /> PROCESS<br /> BEGIN<br /> WAIT UNTIL (clock'EVENT AND clock = '1');<br /> <br /> <br /> IF clr_md = '1' THEN<br /> mdreg <= (OTHERS => '0');<br /> ELSIF load_md = '1' THEN<br /> mdreg <= multiplicand;<br /> ELSE<br /> mdreg <= mdreg;<br /> END IF;<br /> <br /> <br /> IF clr_mr = '1' THEN<br /> mrreg <= (OTHERS => '0');<br /> ELSIF load_mr = '1' THEN<br /> mrreg((k + 1) DOWNTO 1) <= multiplier;<br /> mrreg(0) <= '0';<br /> ELSIF shift_mr = '1' THEN<br /> mrreg <= mrreg SRL 1;<br /> ELSE<br /> mrreg <= mrreg;<br /> END IF;<br /> <br /> <br /> IF clr_pp = '1' THEN<br /> product <= (OTHERS => '0');<br /> ELSIF load_pp = '1' THEN<br /> product((2*k + 1) DOWNTO (k + 1)) <= adderout;<br /> product(k DOWNTO 0) <= product(k DOWNTO 0); <br /> ELSIF shift_pp = '1' THEN<br /> product <= product SRA 1;<br /> ELSE<br /> product <= product;<br /> END IF;<br /> <br /> END PROCESS;<br /> <br /> <br /> <br /> augend <= product((2*k+1) DOWNTO (k+1));<br /> addgen : FOR i IN adderout'RANGE<br /> GENERATE<br /> lsadder : IF i = 0 GENERATE<br /> adderout(i) <= tcbuffout(i) XOR augend(i) XOR comp;<br /> carries(i) <= (tcbuffout(i) AND augend(i)) OR<br /> (tcbuffout(i) AND comp) OR<br /> (comp AND augend(i));<br /> END GENERATE;<br /> otheradder : IF i /= 0 GENERATE<br /> adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);<br /> carries(i) <= (tcbuffout(i) AND augend(i)) OR<br /> (tcbuffout(i) AND carries(i-1)) OR<br /> (carries(i-1) AND augend(i));<br /> END GENERATE;<br /> END GENERATE;<br /> <br /> adder_ovfl <= carries(k-1) XOR carries(k);<br /> <br /> <br /> <br /> tcbuffout <= NOT mdreg WHEN (comp = '1') ELSE mdreg;<br /> <br /> <br /> <br /> PROCESS BEGIN <br /> WAIT UNTIL (clock'EVENT AND clock = '1');<br /> IF boostate < 2*(k + 1) THEN boostate <= boostate + 1;<br /> ELSE boostate <= 0;<br /> END IF;<br /> END PROCESS;<br /> <br /> <br /> <br /> PROCESS(boostate)<br /> BEGIN<br /> <br /> comp <= '0';<br /> clr_mr <= '0';<br /> load_mr <= '0';<br /> shift_mr <= '0';<br /> clr_md <= '0';<br /> load_md <= '0';<br /> clr_pp <= '0';<br /> load_pp <= '0';<br /> shift_pp <= '0';<br /> IF boostate = 0 THEN<br /> load_mr <= '1';<br /> load_md <= '1';<br /> clr_pp <= '1';<br /> ELSIF boostate MOD 2 = 0 THEN <br /> shift_mr <= '1';<br /> shift_pp <= '1';<br /> ELSE --boostate = 1,3,5,7......<br /> IF mrreg(0) = mrreg(1) THEN<br /> NULL; --refresh pp<br /> ELSE<br /> load_pp <= '1'; <br /> END IF;<br /> comp <= mrreg(1); <br /> END IF;<br /> END PROCESS;<br /> <br /> END structural;<br />用max plus2编译显示错误如下:<br />Error:Unkown problem in e:\myproject\booth_multiplier.vhd[%SynPrep-A-UnexpectedCase,UnexpectedCase:"Unexpected value for tOpClass"in iEvalOperation at line 640 of file readexpr.c.] |
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