module Ram(RamAddrH, RamAddrL, RamAddrMSB, RamData,
RamWR, RamRD, RamCS, McuData, McuWR, McuRD, McuRS, xck);
output RamWR; // cpld 与 ram 的写信号
output RamRD; // cpld 与 ram 的读信号
output RamCS; // cpld 与 ram 的片选信号
initial
begin
RamWR=1'b1;
RamRD=1'b1;
RamCS='b0;
RamAddrMSB=1'b0;
end
//////////////////////////////////////////////////
编译是出现如下错误
Error: Verilog HDL Procedural Assignment error at Ram.v(30): illegal Procedural Assignment to nonregister data type "RamWR"
Error: Verilog HDL Procedural Assignment error at Ram.v(31): illegal Procedural Assignment to nonregister data type "RamRD"
Error: Verilog HDL Procedural Assignment error at Ram.v(32): illegal Procedural Assignment to nonregister data type "RamCS"
Error: Verilog HDL Procedural Assignment error at Ram.v(34): illegal Procedural Assignment to nonregister data type "RamAddrMSB"
这是为什么啊? |
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