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请帮帮我,这个程序有一个错误，请大侠帮我改改这个用MAX+plusII仿真谢谢！！library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br /><br />entity countrl is<br /> port(<br /> CLR: in std_logic; <br /> Fa: IN std_logic; <br /> Fb: in std_logic;<br /> Tp:in std_logic; <br /> Tt: buffer std_logic;<br /> phasen:out std_logic<br /> );<br />end;<br />architecture behav of countrl is <br />signal phas: std_logic;<br />begin<br /> process(Tp,CLR,Fa)<br /> begin<br /> if CLR='1' then Tt<='0';<br /> elsif Fa'event and Fa='1' then<br /> Tt<=Tp;<br /> end if;<br /> end process; <br /> <br /> process(fa,fb,clr) <br /> begin<br /> if clr='1' then phas<='0';<br /> else phas<= fa xor fb ;<br /> end if;<br /> end process;<br /> phasen<=Tt and phas; <br /> end behav;<br /> <br /><br /> end if;<br /> end process; <br /> <br /> process(fa,fb,clr) <br /> begin<br /> if clr='1' then phas<='0';<br /> else phas<= fa xor fb ;<br /> end if;<br /> end process;<br /> phasen<=Tt and phas; <br /> end behav;<br /> <br /> <br /> |
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