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现想实现如下功能：<br />输入有两个时钟信号：gate：1Hz方波，clk：40MHz；另一输入是使能信号：en。<br />输出：对40MHz方波进行分频输出方波:dataout。<br />要求：在en=1时，dataout=0；在en=0时，等gate的上升沿来时，dataout开始输出方波，以后等每个gate的上升沿对输出复位一次，使输出与gate的上升沿同步。<br />程序如下：<br />library IEEE;<br />use IEEE.STD_LOGIC_1164.ALL;<br />use IEEE.STD_LOGIC_ARITH.ALL;<br />use IEEE.STD_LOGIC_UNSIGNED.ALL;<br /><br />ENTITY KEYSCAN IS<br /> PORT (<br /> clk : IN std_logic; <br /> gate : IN std_logic; <br /> en : IN std_logic; <br /> dataout : OUT std_logic); <br />END KEYSCAN;<br /><br />ARCHITECTURE arch OF KEYSCAN IS<br />SIGNAL div_cnt : std_logic_vector(3 downto 0);<br />SIGNAL dataout_tmp : std_logic; <br />SIGNAL start : std_logic; <br />BEGIN<br /><br />dataout<=dataout_tmp;<br /><br />PROCESS(en,clk,gate)<br /><br />BEGIN <br /><br /> IF (en= '1') THEN<br /> dataout_tmp<='0';<br /> div_cnt <= "0000";<br /> start<='1';<br /> elsif(en= '0') then<br /> IF (gate'EVENT AND gate = '1') THEN<br /> dataout_tmp<='1';<br /> div_cnt <= "0000";<br /> start<='0';<br /> end if;<br /> end if;<br /> IF(start<='0' and (clk'EVENT AND clk = '1'))then <br /> div_cnt <= div_cnt + 1; <br /> IF (div_cnt="0111") THEN <br /> dataout_tmp<='0';<br /> ELSIF (div_cnt="1111") THEN<br /> dataout_tmp<='1';<br /> end if; <br /> end if;<br /><br />END PROCESS;<br />END arch;<br /><br />提示如下错误：<br /><br />怎么改正，请指点，谢谢！<br /><br />Error (10629): VHDL error at KEYSCAN.vhd(42): can't synthesize logic for statement with conditions that test for the edges of multiple clocks<br /> |
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