现想实现如下功能：
输入有两个时钟信号：gate：1Hz方波，clk：40MHz；另一输入是使能信号：en。
输出：对40MHz方波进行分频输出方波:dataout。
要求：在en=1时，dataout=0；在en=0时，等gate的上升沿来时，dataout开始输出方波，以后等每个gate的上升沿对输出复位一次，使输出与gate的上升沿同步。
程序如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KEYSCAN IS
PORT (
clk : IN std_logic;
gate : IN std_logic;
en : IN std_logic;
dataout : OUT std_logic);
END KEYSCAN;
ARCHITECTURE arch OF KEYSCAN IS
SIGNAL div_cnt : std_logic_vector(3 downto 0);
SIGNAL dataout_tmp : std_logic;
SIGNAL start : std_logic;
BEGIN
dataout<=dataout_tmp;
PROCESS(en,clk,gate)
BEGIN
IF (en= '1') THEN
dataout_tmp<='0';
div_cnt <= "0000";
start<='1';
elsif(en= '0') then
IF (gate'EVENT AND gate = '1') THEN
dataout_tmp<='1';
div_cnt <= "0000";
start<='0';
end if;
end if;
IF(start<='0' and (clk'EVENT AND clk = '1'))then
div_cnt <= div_cnt + 1;
IF (div_cnt="0111") THEN
dataout_tmp<='0';
ELSIF (div_cnt="1111") THEN
dataout_tmp<='1';
end if;
end if;
END PROCESS;
END arch;
提示如下错误：
怎么改正，请指点，谢谢！
Error (10629): VHDL error at KEYSCAN.vhd(42): can't synthesize logic for statement with conditions that test for the edges of multiple clocks
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