library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test_ram is
port
(
data_out: out std_logic_vector(7 downto 0);
wraddr : out std_logic_vector(9 downto 0);
wr_en : out std_logic;
data_in : in std_logic_vector(7 downto 0);
rdaddr : out std_logic_vector(9 downto 0);
rd_en : out std_logic;
clk,reset: in std_logic;
clr : out std_logic
);
end test_ram;
architecture a of test_ram is
signal data_temp:std_logic_vector(7 downto 0):="00000000";
signal addr_temp:std_logic_vector(9 downto 0):="0000000000";
signal write_en:std_logic:='1';
signal read_en:std_logic:='0';
begin
-- write or read judge process
process(reset,clk) is
-- Declaration(s)
begin
if(reset = '1') then
data_temp<="00000000";
addr_temp<="0000000000";
end if;
if(data_temp>100) then
if(write_en='1') then
write_en<='0';
read_en<='1';
elsif(read_en='1') then
write_en<='1';
read_en<='0';
end if;
end if;
end process;
-- data and addr product process
process(reset, clk) is
begin
if(reset = '0') then
if(write_en='1') then
data_temp<=data_temp+1;
addr_temp<=addr_temp+1;
elsif(read_en='1') then
addr_temp<=addr_temp+1;
end if;
else
data_temp<="00000000";
addr_temp<="0000000000";
end if;
end process;
-- out process
process(reset, clk) is
-- Declaration(s)
begin
if(reset = '0') then
if(rising_edge(clk)) then
-- wr_en<=write_en;
end if;
end if;
data_out<=data_temp;
wraddr<=addr_temp;
rdaddr<=addr_temp;
end process;
end a;
编译环境：quartus 7.2
我想用单独的一个进程专门做输出、输入信号的处理。但是已编译就出现这个错误如下（请高人指点，如何在多进程间传递信号）：
Error (10028): Can't resolve multiple constant drivers for net "addr_temp[0]" at test_ram.vhd(57)
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