我在测试EZ－USB FX2的Slave FIFO模式下，采用全手动方式与外部控制器进行数据交换。现在的问题是，将FX2设置成手动时，如何用外部控制器读取数据？数据是自动送到FX2的数据线上，还是需要外部控制器控制那几根口线来读？如果是用外部控制器来控制口线，FX2内的数据什么时候会送到数据线上（FD[7:0]+FB[7:0]）？
void TD_Init( void )
{ // Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
IFCONFIG = 0xCB;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz internal clk rate
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=1 , master samples asynchronous
// GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=11, FX2 in slave FIFO mode
SYNCDELAY; // see TRM section 15.14
REVCTL = 0x03; // use enhanced packet handling
//EP2 512 bulk out 2x
// SYNCDELAY;
// EP2CFG = 0xa2; //Valid = 1; dir = 0(out); type1:0 = 10(bulk); size = 0(512B); bit2 = 0; buf1:0 = 10(2x)
//EP6 512 bulk in 2x
// SYNCDELAY;
// EP6CFG = 0xa2; //11100010B, bulk in, 512, 2x
//使用EP4作为手动输出端点！
SYNCDELAY; //
EP4CFG = 0xa2; // clear valid bit
// SYNCDELAY; //
// EP8CFG = 0xa2; // clear valid bit
//next is reset all the endpoint.
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
//Set FIFO flags to Indexed mode:
//FLAGA ==> Programmed level
//FLAGB ==> FULL
//FLAGC ==> EMPTY
/* SYNCDELAY;
PINFLAGSAB = 0x98; // FLAGA - fixed EP2EF, FLAGB - fixed EP4EF
SYNCDELAY;
PINFLAGSCD = 0xFE; // FLAGC - fixed EP6FF, FLAGD - fixed EP8FF
SYNCDELAY;
*/
//PORTACFG |= 0x80; // FLAGD, set alt. func. of PA7 pin
PORTACFG |= 0x40; // ENABLE SLCE#.
SYNCDELAY;
FIFOPINPOLAR = 0x00; // all signals active low
SYNCDELAY;
//EP2 FIFO config, use 16 bits(WORDWIDE = 1), manual mode
// EP2FIFOCFG = 0x01; //AUTOIN = AUTOOUT = 0; WORDWIDE = 1; ZEROLENIN = 1: enable zero length
SYNCDELAY;
// EP6FIFOCFG = 0x01; //AUTOIN = AUTOOUT = 0; WORDWIDE = 1; ZEROLENIN = 1: enable zero length
SYNCDELAY;
EP4FIFOCFG = 0x01; //AUTOIN = AUTOOUT = 0; WORDWIDE = 1; ZEROLENIN = 1: enable zero length
SYNCDELAY;
// EP8FIFOCFG = 0x01; //AUTOIN = AUTOOUT = 0; WORDWIDE = 1; ZEROLENIN = 1: enable zero length
SYNCDELAY;
// OUT endpoints do NOT come up armed //double buffered.
SYNCDELAY;
OUTPKTEND = 0x82; // arm first buffer by writing OUTPKTEND w/skip=1
SYNCDELAY;
OUTPKTEND = 0x82; // arm second buffer by writing OUTPKTEND w/skip=1
// EP2FIFOBUF[0] = 0x20;
// EP2FIFOBUF[1] = 0x21;
/// EP2FIFOBUF[2] = 0x22;
// EP2FIFOBUF[3] = 0x23;
// EP2FIFOBUF[4] = 0x24;
// EP2FIFOBUF[5] = 0x25;
// EP2FIFOBUF[6] = 0x26;
/* EP2FIFOBUF[7] = 0x27;
EP4FIFOBUF[0] = 0x40;
EP4FIFOBUF[1] = 0x41;
EP4FIFOBUF[2] = 0x42;
EP4FIFOBUF[3] = 0x43;
EP4FIFOBUF[4] = 0x44;
EP4FIFOBUF[5] = 0x45;
EP4FIFOBUF[6] = 0x46;
EP4FIFOBUF[7] = 0x47;
EP6FIFOBUF[0] = 0xAA;
EP6FIFOBUF[1] = 0xAA;
EP6FIFOBUF[2] = 0xAA;
EP6FIFOBUF[3] = 0xAA;
EP6FIFOBUF[4] = 0xAA;
EP6FIFOBUF[5] = 0xAA;
EP6FIFOBUF[6] = 0xAA;
EP6FIFOBUF[7] = 0xAA;
EP8FIFOBUF[0] = 0x55;
EP8FIFOBUF[1] = 0x55;
EP8FIFOBUF[2] = 0x55;
EP8FIFOBUF[3] = 0x55;
EP8FIFOBUF[4] = 0x55;
EP8FIFOBUF[5] = 0x55;
EP8FIFOBUF[6] = 0x55;
EP8FIFOBUF[7] = 0x55; */
}
void TD_Poll(void) //XHW
{
if(!(EP2468STAT & 0x04))
{
OUTPKTEND = 0x02;
}
}
再请问高手，这段程序是否有问题？谢谢！ |
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