LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY cnt6 IS
PORT(reset,en,clk:IN STD_ULOGIC;
carry:OUT STD_ULOGIC;
q:OUT STD_ULOGIC_VECTOR(2 DOWNTO 0);
END cnt6;
ARCHITECTURE rtl OF cnt6 IS
SIGNALqs:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ca:STD_ULOGIC;
BEGIN
PROCESS(clk)
VARIABLE q6:INTEGER;
BEGIN
IF (clk'EVENT ADN clk='1') THEN
IF(reset='1') THEN
q6:=0;
ELSIF (en='1') THEN
IF(q6=5) THEN
q6:=0;
ca<='0';
ELSIF(q6=4) THEN
q6:=q6+1;
ca<='1';
ELSE
q6:=q6+1;
ca<='0';
END IF;
END IF;
END IF;
qs<=CONV_STD_LOGIC_VECTOR(q6,3);
q<=TO_STDULOGICVECTOR(qs);
END PROCESS;
PROCESS(ca,en)
BEGIN
carry<=ca AND en;
END PROCESS;
END rtl; |
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