我是想用McBSP接收一个帧信号为8K，时钟为4.096M的2倍E1的信号。
想法是帧信号和时钟都由外部提供，每帧64个8比特数据，A-law压扩。
DMA设置为64个元素，接收/发送完64个数据产生中断。
我搞了好几天还是不行。
似乎是串口没有配置对，明明配置成一帧64个元素，用rrdy/xrdy来触发中断，结果一帧只来了一个中断，也就是说只收到一个数据，其它63个都没有了？不知道怎么回事。
我的DMA也一直工作不正常，中断只能进去一次，后面就进不去了。
现在天天找问题，头晕脑胀啊。
我的配置文件放在下面大家看看。
因为怕那个8k的时钟对不齐，所以先初始化一个由FRAME触发的中断，然后在这个中断程序里面重新初始化串口和DMA。
发现5502真是很麻烦。
/********************************************************************************/
/* 文件名: GSBPerConfg.h */
/* 创建日期: 08/06/2007 */
/* 功能描述: 外设寄存器配置参数 */
/* Author ： whj */
/********************************************************************************/
#ifndef _GSB_PER_CNFG
#define _GSB_PER_CNFG
#include <csl.h>
#include <csl_pll.h>
#include <csl_chip.h>
#include <csl_irq.h>
#include <csl_gpt.h>
#include <csl_chip.h>
#include <csl_mcbsp.h>
#include <csl_hpi.h>
#include <csl_dma.h>
//一帧中的时隙数
#define TS 64
/* Define transmit and receive buffers */
#pragma DATA_SECTION(xmt,"dmaMem")
Int16 xmt[TS];
#pragma DATA_SECTION(rcv,"dmaMem")
Int16 rcv[TS];
/*64 bit general purpose timer */
/* Define and initialize the GPT module configuration structure */
GPT_Config MyGptConfig = {
0, //Emulation management register
0, //GPIO interrupt control register
0, //GPIO enable register
0, //GPIO direction register
0, //GPIO data register
0xB9EF, //Timer period register 1
0x05F5, //Timer period register 2
0, //Timer period register 3
0, //Timer period register 4
GPT_GPTCTL1_RMK( //Timer control register 1
GPT_GPTCTL1_TIEN_NOT_GATED,
GPT_GPTCTL1_CLKSRC_VBUS,
GPT_GPTCTL1_ENAMODE_CONTINUOUS,
GPT_GPTCTL1_PWID_INACTIVE_1CYCLE,
GPT_GPTCTL1_CP_CLOCK_MODE,
GPT_GPTCTL1_INVIN_DONT_INVERT_OUTPUT,
GPT_GPTCTL1_INVOUT_DONT_INVERT_OUTPUT
),
GPT_GPTCTL2_RMK( //Timer control register 2
GPT_GPTCTL2_TIEN_NOT_GATED,
GPT_GPTCTL2_CLKSRC_VBUS,
GPT_GPTCTL2_ENAMODE_CONTINUOUS,
GPT_GPTCTL2_PWID_INACTIVE_1CYCLE,
GPT_GPTCTL2_CP_CLOCK_MODE,
GPT_GPTCTL2_INVIN_DONT_INVERT_OUTPUT,
GPT_GPTCTL2_INVOUT_DONT_INVERT_OUTPUT
),
GPT_GPTGCTL1_RMK( //Global timer control register
GPT_GPTGCTL1_PSC34_DEFAULT,
GPT_GPTGCTL1_TIMMODE_DEFAULT,
GPT_GPTGCTL1_TIM34RS_NOT_IN_RESET,
GPT_GPTGCTL1_TIM12RS_NOT_IN_RESET
)
};
/********** McBSP Config *****************/
MCBSP_Config GSBMcBspConfigInit = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, /* Digital loopback Disable */
MCBSP_SPCR1_RJUST_RZF, /* Right justify the data and zero fill the MSBs. */
MCBSP_SPCR1_CLKSTP_DISABLE, /*Clock stop mode is disabled. only used in SPI protocol */
MCBSP_SPCR1_DXENA_OFF, /*DX delay enabler off */
MCBSP_SPCR1_ABIS_DISABLE, /* */
MCBSP_SPCR1_RINTM_FRM, /* Receive Ready interrupt*/
MCBSP_SPCR1_RSYNCERR_NO, /* No error */
MCBSP_SPCR1_RFULL_YES, /* Read Only */
MCBSP_SPCR1_RRDY_YES, /* Read Only */
MCBSP_SPCR1_RRST_ENABLE /* Not in Reset */
),
//0x01,
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, /*The McBSP transmit and receive clocks are affected as determined by the */
/*SOFT bit. */
MCBSP_SPCR2_SOFT_YES, /* The McBSP transmit clock stops after completion of the current
serial word transfer. The McBSP receive clock is not affected.*/
MCBSP_SPCR2_FRST_FSG, /* 1: frame-sync logic not in Reset*/
MCBSP_SPCR2_GRST_CLKG, /* 1: Not in reset */
MCBSP_SPCR2_XINTM_XRDY, /* interrupt is sent when each one word is tansmitted completely*/
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XEMPTY_YES, /*Read Only */
MCBSP_SPCR2_XRDY_YES, /*Read Only */
MCBSP_SPCR2_XRST_ENABLE /* enable transmitter */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(1), /* 1 words per receive frame */
MCBSP_RCR1_RWDLEN1_8BIT /* receive word length 8 bit */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* signle phase */
MCBSP_RCR2_RFRLEN2_OF(0), /* phase 2 not used */
MCBSP_RCR2_RWDLEN2_8BIT , /* no meaning */
MCBSP_RCR2_RCOMPAND_ALAW, /*ALAW companding in reception */
MCBSP_RCR2_RFIG_YES, /* An unexpected FSR pulse causes the receiver to */
/* discard the contents of RSR[1,2] in favor of the new incoming data.*/
MCBSP_RCR2_RDATDLY_1BIT /* rcv 1 bit delay */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(1), /* Transmit frame length 1 (1 to 128 words). 64 words per frame */
MCBSP_XCR1_XWDLEN1_8BIT /* transmit word length1 8 bit */
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* The transmit frame has only one phase, phase 1 */
MCBSP_XCR2_XFRLEN2_OF(0), /* phase 2 not used */
MCBSP_XCR2_XWDLEN2_8BIT, /* Transmit word length 2, no used */
MCBSP_XCR2_XCOMPAND_ALAW, /* ALAW companding in transmission */
MCBSP_XCR2_XFIG_YES, /* Unexpected Transmit Frame-Synch Pulse */
MCBSP_XCR2_XDATDLY_1BIT /* xmt 1 bit delay */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0), /* Frame-sync(FSG) pulse width is 1(0+1) CLKG cycles */
MCBSP_SRGR1_CLKGDV_OF(0) /* CLKG frequency = (Input clock frequency) / (CLKGDV + 1), CLKG equals to CLKR/CLKX */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* Always write 0 to this bit on 5502,NO this function on 5502 */
MCBSP_SRGR2_CLKSP_RISING, /* we don't use CLKS input, don't care this bit*/
MCBSP_SRGR2_CLKSM_CLKS,/* 0 : input clock for sample rate generator is Signal on CLKS/CLKR pin,depend on SCLKME */
MCBSP_SRGR2_FSGM_FSG, /* the transmitter uses frame-sync pulses generated by the sample rate generator */
MCBSP_SRGR2_FPER_OF(511) /* Frame-sync period is 512 CLKG cycles*/
),
MCBSP_MCR1_DEFAULT, /* we don't use multiple channels*/
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
0, /* IDLEEN, 5502 should write to 0*/
MCBSP_PCR_XIOEN_SP, /*The CLKX, FSX, DX, and CLKS pins are serial port pins*/
MCBSP_PCR_RIOEN_SP, /*The CLKR, FSR, DR, and CLKS pins are serial port pins*/
MCBSP_PCR_FSXM_EXTERNAL, /*Transmit frame synchronization is supplied by an external source via the FSX pin.*/
MCBSP_PCR_FSRM_EXTERNAL, /*Receive frame synchronization is supplied by an external source via the FSR pin*/
MCBSP_PCR_SCLKME_BCLK, /*1 :The input clock for the sample rate generator is taken from the CLKR pin */
/*cause the value of the CLKSM bit of SRGR2 is 0 */
MCBSP_PCR_CLKSSTAT_0, /* CLKS pin status bit. 5502 doesn't have this pin */
MCBSP_PCR_DXSTAT_0, /* DX pin status bit. */
MCBSP_PCR_DRSTAT_0, /* DR pin status bit. Not GPIO, no meaning here */
MCBSP_PCR_CLKXM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKX pin. */
MCBSP_PCR_CLKRM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKR pin. */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* Transmit frame-sync pulses are active low. */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* Receive frame-sync pulses are active low. */
MCBSP_PCR_CLKXP_RISING, /* Transmit data is driven on the rising edge of CLKX，发送上升沿 */
MCBSP_PCR_CLKRP_FALLING /* When the CLKR pin is configured as an input, the external CLKR is not */
/* inverted before being used internally and the receive data is sampled on the */
/* falling edge of CLKR. */
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
/********** McBSP Config *****************/
MCBSP_Config GSBMcBspConfig = {
// MCBSP_SPCR1_RMK(
// MCBSP_SPCR1_DLB_OFF, /* Digital loopback Disable */
// MCBSP_SPCR1_RJUST_RZF, /* Right justify the data and zero fill the MSBs. */
// MCBSP_SPCR1_CLKSTP_DISABLE, /*Clock stop mode is disabled. only used in SPI protocol */
// MCBSP_SPCR1_DXENA_OFF, /*DX delay enabler off */
// MCBSP_SPCR1_ABIS_DISABLE, /* */
// MCBSP_SPCR1_RINTM_RRDY, /* Receive Ready interrupt*/
// MCBSP_SPCR1_RSYNCERR_NO, /* No error */
// MCBSP_SPCR1_RFULL_YES, /* Read Only */
// MCBSP_SPCR1_RRDY_YES, /* Read Only */
// MCBSP_SPCR1_RRST_ENABLE /* Not in Reset */
// ),
0x01,
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, /*The McBSP transmit and receive clocks are affected as determined by the */
/*SOFT bit. */
MCBSP_SPCR2_SOFT_YES, /* The McBSP transmit clock stops after completion of the current
serial word transfer. The McBSP receive clock is not affected.*/
MCBSP_SPCR2_FRST_FSG, /* 1: frame-sync logic not in Reset*/
MCBSP_SPCR2_GRST_CLKG, /* 1: Not in reset */
MCBSP_SPCR2_XINTM_XRDY, /* interrupt is sent when each one word is tansmitted completely*/
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XEMPTY_YES, /*Read Only */
MCBSP_SPCR2_XRDY_YES, /*Read Only */
MCBSP_SPCR2_XRST_ENABLE /* enable transmitter */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(TS), /* 64 words per receive frame */
MCBSP_RCR1_RWDLEN1_8BIT /* receive word length 8 bit */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* signle phase */
MCBSP_RCR2_RFRLEN2_OF(0), /* phase 2 not used */
MCBSP_RCR2_RWDLEN2_8BIT , /* no meaning */
MCBSP_RCR2_RCOMPAND_ALAW, /*ALAW companding in reception */
MCBSP_RCR2_RFIG_YES, /* An unexpected FSR pulse causes the receiver to */
/* discard the contents of RSR[1,2] in favor of the new incoming data.*/
MCBSP_RCR2_RDATDLY_1BIT /* rcv 1 bit delay */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(TS), /* Transmit frame length 1 (1 to 128 words). 64 words per frame */
MCBSP_XCR1_XWDLEN1_8BIT /* transmit word length1 8 bit */
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* The transmit frame has only one phase, phase 1 */
MCBSP_XCR2_XFRLEN2_OF(0), /* phase 2 not used */
MCBSP_XCR2_XWDLEN2_8BIT, /* Transmit word length 2, no used */
MCBSP_XCR2_XCOMPAND_ALAW, /* ALAW companding in transmission */
MCBSP_XCR2_XFIG_YES, /* Unexpected Transmit Frame-Synch Pulse */
MCBSP_XCR2_XDATDLY_1BIT /* xmt 1 bit delay */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0), /* Frame-sync(FSG) pulse width is 1(0+1) CLKG cycles */
MCBSP_SRGR1_CLKGDV_OF(0) /* CLKG frequency = (Input clock frequency) / (CLKGDV + 1), CLKG equals to CLKR/CLKX */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* Always write 0 to this bit on 5502,NO this function on 5502 */
MCBSP_SRGR2_CLKSP_RISING, /* we don't use CLKS input, don't care this bit*/
MCBSP_SRGR2_CLKSM_CLKS,/* 0 : input clock for sample rate generator is Signal on CLKS/CLKR pin,depend on SCLKME */
MCBSP_SRGR2_FSGM_FSG, /* the transmitter uses frame-sync pulses generated by the sample rate generator */
MCBSP_SRGR2_FPER_OF(511) /* Frame-sync period is 512 CLKG cycles*/
),
MCBSP_MCR1_DEFAULT, /* we don't use multiple channels*/
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
0, /* IDLEEN, 5502 should write to 0*/
MCBSP_PCR_XIOEN_SP, /*The CLKX, FSX, DX, and CLKS pins are serial port pins*/
MCBSP_PCR_RIOEN_SP, /*The CLKR, FSR, DR, and CLKS pins are serial port pins*/
MCBSP_PCR_FSXM_EXTERNAL, /*Transmit frame synchronization is supplied by an external source via the FSX pin.*/
MCBSP_PCR_FSRM_EXTERNAL, /*Receive frame synchronization is supplied by an external source via the FSR pin*/
MCBSP_PCR_SCLKME_BCLK, /*1 :The input clock for the sample rate generator is taken from the CLKR pin */
/*cause the value of the CLKSM bit of SRGR2 is 0 */
MCBSP_PCR_CLKSSTAT_0, /* CLKS pin status bit. 5502 doesn't have this pin */
MCBSP_PCR_DXSTAT_0, /* DX pin status bit. */
MCBSP_PCR_DRSTAT_0, /* DR pin status bit. Not GPIO, no meaning here */
MCBSP_PCR_CLKXM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKX pin. */
MCBSP_PCR_CLKRM_INPUT, /* The transmitter gets its clock signal from an external source via the CLKR pin. */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* Transmit frame-sync pulses are active low. */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* Receive frame-sync pulses are active low. */
MCBSP_PCR_CLKXP_RISING, /* Transmit data is driven on the rising edge of CLKX，发送上升沿 */
MCBSP_PCR_CLKRP_FALLING /* When the CLKR pin is configured as an input, the external CLKR is not */
/* inverted before being used internally and the receive data is sampled on the */
/* falling edge of CLKR. */
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
/* Create DMA Receive Side Configuration */
/* DMACSDP dstben == 0 */
/* dstpack == 0 */
/* dst == 0 */
/* srcben == 0 */
/* srcpack == 0 */
/* src == 5 */
/* datatype == 1 */
/* */
/* DMACCR dstamode == 1 */
/* srcamode == 0 */
/* endprog == 0 */
/* repeat == 0 */
/* autoinit == 1 */
/* en == 0 */
/* prio == 0 */
/* fs == 0 */
/* sync == 0 */
/* */
/* DMACICR blockie == 0 */
/* lastie == 0 */
/* frameie == 1 */
/* firsthalfie == 0 */
/* dropie == 0 */
/* timeoutie == 0 */
DMA_Config dmaRcvConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST, /* dest NO burst */
DMA_DMACSDP_DSTPACK_OFF, /* DST Packing disabled */
DMA_DMACSDP_DST_DARAM, /* DST is DARAM */
DMA_DMACSDP_SRCBEN_NOBURST, /* source NO burst */
DMA_DMACSDP_SRCPACK_OFF, /* source Packing disabled*/
DMA_DMACSDP_SRC_PERIPH, /* source is PERIPH, McBSP0(RCV)*/
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACSDP */
DMA_DMACCR_RMK( /* chanel control register */
DMA_DMACCR_DSTAMODE_DBLINDX, /*After each element transfer, the address is incremented according to the selected data type:*/
DMA_DMACCR_SRCAMODE_CONST, /*Constant address*/
DMA_DMACCR_ENDPROG_ON, /* 1 */
DMA_DMACCR_REPEAT_ON, /*Repeat only if ENDPROG = 1*/
DMA_DMACCR_AUTOINIT_ON, /*Auto-initialization is enabled*/
DMA_DMACCR_EN_START, /*1, Channel is enabled*/
DMA_DMACCR_PRIO_LOW, /* */
DMA_DMACCR_FS_ELEMENT, /* event occurs, one element transfered */
DMA_DMACCR_SYNC_REVT0 /* McBSP 0 receive event */
), /* DMACCR */
DMA_DMACICR_RMK( /* interrupt control register */
DMA_DMACICR_BLOCKIE_OFF, /* address error interrupt off */
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON, /* when all of current frame transfer complete, send int to cpu */
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL, lower part, Data Receive Register 1, McBSP #0 */
0, /* DMACSSAU source start address upper part*/
(DMA_AdrPtr)&rcv[0], /* DMACDSAL; Destination Start Address Registers lower part */
0, /* DMACDSAU upper part*/
(TS-1), /* DMACEN; numbr of element per Frame */
1, /* DMACFN; frame number per block */
0, /* DMACFI; source frame index */
0, /* DMACEI; source element index */
0, |
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