照书上的一个例子原封不动的敲了上去，愣是编译不过去，请大家帮忙看看哪的问题。提示：error:current license file support does not include the 'vhdl design entry'application or feature.
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.All
ENTITY fredevider Is
PORT (Clock:IN Std_Logic;
Clkout:OUT Std_Logic );
END fredevider;
ARCHITECTURE Behavior OF fredevider IS
SIGNAL Clk:Std_Logic;
BEGIN
PROCESS(Clock)
BEGIN
IF rising_edge(Clock) THEN
Clk<=NOT Clk;
END IF;
END PROCESS;
Clkout<=Clk;
END Behavior;
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