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照书上的一个例子原封不动的敲了上去，愣是编译不过去，请大家帮忙看看哪的问题。提示：error:current license file support does not include the 'vhdl design entry'application or feature.<br />LIBRARY IEEE;<br />USE IEEE.Std_Logic_1164.All<br /><br />ENTITY fredevider Is<br />PORT (Clock:IN Std_Logic;<br /> Clkout:OUT Std_Logic );<br />END fredevider;<br /><br />ARCHITECTURE Behavior OF fredevider IS<br />SIGNAL Clk:Std_Logic;<br />BEGIN<br /> PROCESS(Clock)<br /> BEGIN<br /> IF rising_edge(Clock) THEN<br /> Clk<=NOT Clk;<br /> END IF;<br /> END PROCESS;<br /> Clkout<=Clk;<br />END Behavior;<br /> |
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楼主
