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LIBRARY ieee;<br />USE ieee.std_logic_1164.all;<br />USE ieee.std_logic_arith.all;<br />USE ieee.std_logic_unsigned.all;<br />ENTITY counter IS<br /> GENERIC<br /> (<br /> divisor : INTEGER:= 24000000; <br /> inner_counter_width : INTEGER:= 32; <br /> unit : STD_LOGIC_VECTOR(3 downto 0):= "1111"<br /> );<br /> <br /> PORT<br /> (<br /> clock : IN STD_LOGIC;<br /> reset : IN STD_LOGIC;<br /> counter : BUFFER STD_LOGIC_VECTOR(3 downto 0);<br /> carrier : BUFFER STD_LOGIC<br /> );<br /> <br />END counter;<br /><br />ARCHITECTURE counter_architecture OF counter IS <br />BEGIN<br /> <br /> PROCESS(clock)<br /> VARIABLE delay_counter : INTEGER RANGE 0 TO divisor;<br /> BEGIN <br /> IF (reset = '1') THEN<br /> carrier <= '1';<br /> counter <= "0000";<br /> delay_counter := 0; <br /> ELSE<br /> IF(clock = '1' AND clock'EVENT) THEN<br /> IF (delay_counter = divisor/2-1) THEN<br /> carrier <= NOT carrier;<br /> --var_carrier := NOT var_carrier;<br /> --carrier <= delay_counter[0];<br /> delay_counter := 0; <br /> ELSE<br /> delay_counter := delay_counter+1;<br /> END IF;<br /> <br /> IF (counter = unit) THEN<br /> counter <= "0000";<br /> ELSE<br /> counter <= counter+1;<br /> END IF;<br /> <br /> END IF;<br /> END IF;<br /> <br /> <br /> END PROCESS;<br /><br />END counter_architecture;<br />晶振是66mhz的，divisor是分频系数，carrier是时间输出，我算了算，66/24=2.75hz就是0.36s,那么输出应该是0.36s啊，为什么是1s？ |
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