我在一个工程中添加了一个testbench.v文件，编译时报错误
** Error: E:/MODELSIM/source/mux/func/testbench.v(1): near "
": syntax error, unexpected $undefined, expecting "class"
源代码如下：
'include "muxtwo.v"
module testbench;
reg ain, bin, select;
reg clock;
wire outw;
initial begin
ain = 0;
bin = 0;
select = 0;
clock = 0;
end
always #50 clock =~clock;
always @(posedge clock) begin
#1 ain = {$random}%2;
#3 bin = {$random}%2;
end
always #10000 select = !select;
muxtwo m(.out(outw),.a(ain),.b(bin),.sl(select));
endmodule
muxtwo是一个二选一的数据选择器。夏老师的书上的一个范例，可惜编译的时候就是通不过，我是第一次接触testbench，请各位帮忙看下什么原因。 |
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