LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY complement is
PORT (datain : IN STD_LOGIC_VECTOR( 15 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0));
END complement;
ARCHITECTURE a of complement is
SIGNAL temp : STD_LOGIC_VECTOR( 15 DOWNTO 0);
BEGIN
temp <= NOT datain;
dataout <= temp + "0000000000000001";
END a;
这段代码问题出在哪？
下面是maxplus给出的错误原因：
13行，can not interpret subprogram call . |
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