从网上下载了一个UART程序，可以综合，但在进入布局布线时出现的问题：
Actel Designer Software
Version: 8.5.0.34
Release: v8.5
Netlist Reading Time = 0.0 seconds
Imported the files:
E:\cpld_program\uart1\uart\synthesis\uart_tb.edn
E:\cpld_program\uart1\uart\synthesis\uart_tb_sdc.sdc
The Import command succeeded ( 00:00:01 )
Info: The design E:\cpld_program\uart1\uart\designer\impl1\uart_tb.adb was last modified by software version 8.5.0.34.
Opened an existing Libero design E:\cpld_program\uart1\uart\designer\impl1\uart_tb.adb.
'BA_NAME' set to 'uart_tb_ba'
The Execute Script command succeeded ( 00:00:00 )
Checking for software updates...
=====================================================================
Parameters used to run compile:
===============================
Family : ProASIC3
Device : A3P030
Package : 100 VQFP
Source : E:\cpld_program\uart1\uart\synthesis\uart_tb.edn
E:\cpld_program\uart1\uart\synthesis\uart_tb_sdc.sdc
Format : EDIF
Topcell : uart_tb
Speed grade : -2
Temp : 0:25:70
Voltage : 1.58:1.50:1.42
Keep Existing Physical Constraints : No
Keep Existing Timing Constraints : Yes
pdc_abort_on_error : Yes
pdc_eco_display_unmatched_objects : No
pdc_eco_max_warnings : 10000
demote_globals : No
promote_globals : No
localclock_max_shared_instances : 12
localclock_buffer_tree_max_fanout : 12
combine_register : No
delete_buffer_tree : No
report_high_fanout_nets_limit : 10
=====================================================================
Compile starts ...
Netlist Optimization Report
===========================
Optimized macros:
- Dangling net drivers: 0
- Buffers: 0
- Inverters: 0
- Tieoff: 0
- Logic combining: 0
Total macros optimized 0
Error: CMP010: A design must contain at least one net.
There were 1 error(s) and 0 warning(s) in this design.
The Compile command failed ( 00:00:00 )
从这些提示看来，已经调入了*.edn文件！！·
请各位指点！！ |
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