DCD config:
/*
* Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of spi, sd, sata
* the board has no nand and eimnor
* spinor: flash_offset: 0x0400
* sata: flash_offset: 0x0400
* sd/mmc: flash_offset: 0x0400
*/
/* the same flash_offset as sd */
BOOT_FROM sd
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF 0x2000
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
//=============================================================================
// Enable all clocks (they are disabled by ROM code)
//=============================================================================
DATA 4, 0x020c4068, 0xffffffff
DATA 4, 0x020c406c, 0xffffffff
DATA 4, 0x020c4070, 0xffffffff
DATA 4, 0x020c4074, 0xffffffff
DATA 4, 0x020c4078, 0xffffffff
DATA 4, 0x020c407c, 0xffffffff
DATA 4, 0x020c4080, 0xffffffff
DATA 4, 0x020c4084, 0xffffffff
DATA 4, 0x020c4018, 0x00060324 //DDR clk to 400MHz
// Switch PL301_FAST2 to DDR Dual-channel mapping
//setmem /32 0x00B00000 = 0x1
DATA 4 0x00b00000 0x00000001
//=============================================================================
// IOMUX
//=============================================================================
//DDR IO TYPE:
DATA 4, 0x020e0798, 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DATA 4, 0x020e0758, 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
DATA 4, 0x020e0588, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
DATA 4, 0x020e0594, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//ADDRESS:
DATA 4, 0x020e056c, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DATA 4, 0x020e0578, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DATA 4, 0x020e074c, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
DATA 4, 0x020e057c, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DATA 4, 0x020e058c, 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
DATA 4, 0x020e059c, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
DATA 4, 0x020e05a0, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
DATA 4, 0x020e078c, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
DATA 4, 0x020e0750, 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DATA 4, 0x020e05a8, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
DATA 4, 0x020e05b0, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
DATA 4, 0x020e0524, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
DATA 4, 0x020e051c, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
DATA 4, 0x020e0518, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
DATA 4, 0x020e050c, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
DATA 4, 0x020e05b8, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
DATA 4, 0x020e05c0, 0x00003038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
DATA 4, 0x020e0774, 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DATA 4, 0x020e0784, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B0DS
DATA 4, 0x020e0788, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B1DS
DATA 4, 0x020e0794, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B2DS
DATA 4, 0x020e079c, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B3DS
DATA 4, 0x020e07a0, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B4DS
DATA 4, 0x020e07a4, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B5DS
DATA 4, 0x020e07a8, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B6DS
DATA 4, 0x020e0748, 0x00000038 // IOMUXC_SW_PAD_CTL_GRP_B7DS
DATA 4, 0x020e05ac, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4, 0x020e05b4, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DATA 4, 0x020e0528, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DATA 4, 0x020e0520, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
DATA 4, 0x020e0514, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
DATA 4, 0x020e0510, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
DATA 4, 0x020e05bc, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
DATA 4, 0x020e05c4, 0x00000038 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: EDB8132B4PM
// Clock Freq.: 400MHz
// MMDC channels: MMDC0 & MMDC1
// Density per CS in Gb: 4
// Chip Selects used: 2
// Number of Banks: 8
// Row address: 14
// Column address: 10
// Data bus width 2x32
//=============================================================================
DATA 4, 0x021b001c, 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DATA 4, 0x021b401c, 0x00008000 // MMDC1_MDSCR, set the Configuration request bit during MMDC set up
DATA 4, 0x021b085c, 0x1B4700C7 //MMDC0_MPZQLP2CTL,LPDDR2 ZQ params
DATA 4, 0x021b485c, 0x1B4700C7 //MMDC1_MPZQLP2CTL,LPDDR2 ZQ params
//=============================================================================
// Calibration setup.
//=============================================================================
DATA 4, 0x021b0800, 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
//ca bus abs delay
DATA 4, 0x021b0890, 0x00500000 // values of 20,40,50,60,7f tried. no difference seen
DATA 4, 0x021b4890, 0x00500000 // values of 20,40,50,60,7f tried. no difference seen
//Read calibration
DATA 4, 0x021b0848, 0x3C383A36 // MPRDDLCTL PHY0
DATA 4, 0x021b4848, 0x3A38343E // MPRDDLCTL PHY1
//Write calibration
DATA 4, 0x021b0850, 0x34343636 // MPWRDLCTL PHY0
DATA 4, 0x021b4850, 0x38283A34 // MPWRDLCTL PHY1
//dqs gating dis
DATA 4, 0x021b083c, 0x20000000
DATA 4, 0x021b0840, 0x00000000
DATA 4, 0x021b483c, 0x20000000
DATA 4, 0x021b4840, 0x00000000
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
DATA 4, 0x021b081c, 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
DATA 4, 0x021b0820, 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
DATA 4, 0x021b0824, 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
DATA 4, 0x021b0828, 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
DATA 4, 0x021b481c, 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
DATA 4, 0x021b4820, 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
DATA 4, 0x021b4824, 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
DATA 4, 0x021b4828, 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
//write data bit delay: (3 is the reccommended default value, although out of reset value is 0)
DATA 4, 0x021b082c, 0xF3333333 // DDR_PHY_P0_MPREDQBY0DL3
DATA 4, 0x021b0830, 0xF3333333 // DDR_PHY_P0_MPREDQBY1DL3
DATA 4, 0x021b0834, 0xF3333333 // DDR_PHY_P0_MPREDQBY2DL3
DATA 4, 0x021b0838, 0xF3333333 // DDR_PHY_P0_MPREDQBY3DL3
DATA 4, 0x021b482c, 0xF3333333 // DDR_PHY_P1_MPREDQBY0DL3
DATA 4, 0x021b4830, 0xF3333333 // DDR_PHY_P1_MPREDQBY1DL3
DATA 4, 0x021b4834, 0xF3333333 // DDR_PHY_P1_MPREDQBY2DL3
DATA 4, 0x021b4838, 0xF3333333 // DDR_PHY_P1_MPREDQBY3DL3
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
//DATA 4, 0x021b08c0, 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
//DATA 4, 0x021b48c0, 0x24911492
// Complete calibration by forced measurement:
DATA 4, 0x021b08b8, 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
DATA 4, 0x021b48b8, 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================
// Channel0 - startng address 0x80000000
DATA 4, 0x021b0004, 0x00020036 // MMDC0_MDPDC
DATA 4, 0x021b0008, 0x00000000 // MMDC0_MDOTC
DATA 4, 0x021b000c, 0x33374135 // MMDC0_MDCFG0
DATA 4, 0x021b0010, 0x00100A83 // MMDC0_MDCFG1
DATA 4, 0x021b0014, 0x00000093 // MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4, 0x021b0018, 0x0000174C // MMDC0_MDMISC
DATA 4, 0x021b001c, 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DATA 4, 0x021b002c, 0x0F9F26D2 // MMDC0_MDRWD
DATA 4, 0x021b0030, 0x00000010 // MMDC0_MDOR
DATA 4, 0x021b0038, 0x00190778 // MMDC0_MDCFG3LP
//DATA 4, 0x021b0040, 0x0000004F // Chan0 CS0_END
DATA 4, 0x021b0040, 0x00000053 // Chan0 CS0_END
DATA 4, 0x021b0400, 0x11420000 // MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled
DATA 4, 0x021b0000, 0xC3110000 // MMDC0_MDCTL
// Channel1 - starting address 0x10000000
DATA 4, 0x021b4004, 0x00020036 // MMDC1_MDPDC
DATA 4, 0x021b4008, 0x00000000 // MMDC1_MDOTC
DATA 4, 0x021b400c, 0x33374135 // MMDC1_MDCFG0
DATA 4, 0x021b4010, 0x00100A83 // MMDC1_MDCFG1
DATA 4, 0x021b4014, 0x00000093 // MMDC1_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
DATA 4, 0x021b4018, 0x0000174C // MMDC1_MDMISC
DATA 4, 0x021b401c, 0x00008000 // MMDC1_MDSCR, set the Configuration request bit during MMDC set up
DATA 4, 0x021b402c, 0x0F9F26D2 // MMDC1_MDRWD
DATA 4, 0x021b4030, 0x00000010 // MMDC1_MDOR
DATA 4, 0x021b4038, 0x00190778 // MMDC1_MDCFG3LP
DATA 4, 0x021b4040, 0x00000017 // Chan1 CS0_END
DATA 4, 0x021b4040, 0x00000013 // Chan1 CS0_END
//DATA 4, 0x021b4400, 0x11420000 // MMDC1_MAARCR ADOPT optimized priorities. Dyn jump disabled
DATA 4, 0x021b4000, 0xC3110000 // MMDC1_MDCTL
// Channel0 : Configure DDR device:
//CS0
DATA 4, 0x021b001c, 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
DATA 4, 0x021b001c, 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
DATA 4, 0x021b001c, 0x82018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=c2
DATA 4, 0x021b001c, 0x06028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4
DATA 4, 0x021b001c, 0x01038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6
//CS1
DATA 4, 0x021b001c, 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0
DATA 4, 0x021b001c, 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff
DATA 4, 0x021b001c, 0x82018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=c2
DATA 4, 0x021b001c, 0x06028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4
DATA 4, 0x021b001c, 0x01038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=2.drive=240/6
// Channel1 : Configure DDR device:
//CS0
DATA 4, 0x021b401c, 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0
DATA 4, 0x021b401c, 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff
DATA 4, 0x021b401c, 0x82018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=c2
DATA 4, 0x021b401c, 0x06028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4
DATA 4, 0x021b401c, 0x01038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6
//CS1
DATA 4, 0x021b401c, 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0
DATA 4, 0x021b401c, 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff
DATA 4, 0x021b401c, 0x82018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=c2
DATA 4, 0x021b401c, 0x06028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4
DATA 4, 0x021b401c, 0x01038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=2.drive=240/6
DATA 4, 0x021b0800, 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
DATA 4, 0x021b0020, 0x00001800 // MMDC0_MDREF
DATA 4, 0x021b4020, 0x00001800 // MMDC1_MDREF
DATA 4, 0x021b0818, 0x00000000 // DDR_PHY_P0_MPODTCTRL
DATA 4, 0x021b4818, 0x00000000 // DDR_PHY_P1_MPODTCTRL
DATA 4, 0x021b0004, 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled
DATA 4, 0x021b4004, 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled
DATA 4, 0x021b0404, 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
DATA 4, 0x021b4404, 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
DATA 4, 0x021b001c, 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
DATA 4, 0x021b401c, 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
/***
The following lines are from sabresd config and need to be changed according
to Yilian configurations.
***/
/* set the default clock gate to save power */
// DATA 4, 0x020c4068, 0x00C03F3F
// DATA 4, 0x020c406c, 0x0030FC03
// DATA 4, 0x020c4070, 0x0FFFC000
// DATA 4, 0x020c4074, 0x3FF00000
// DATA 4, 0x020c4078, 0x00FFF300
// DATA 4, 0x020c407c, 0x0F0000F3
// DATA 4, 0x020c4080, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
// DATA 4, 0x020e0010, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
// DATA 4, 0x020e0018, 0x007F007F
// DATA 4, 0x020e001c, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
// DATA 4, 0x020c4060, 0x000000fb
#endif
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